1 /* 2 * 3 * (C) Copyright 2000-2003 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 * 6 * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc. 7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #include <common.h> 29 #include <asm/processor.h> 30 31 #include <asm/immap.h> 32 #include <asm/io.h> 33 34 DECLARE_GLOBAL_DATA_PTR; 35 36 /* PLL min/max specifications */ 37 #define MAX_FVCO 500000 /* KHz */ 38 #define MAX_FSYS 80000 /* KHz */ 39 #define MIN_FSYS 58333 /* KHz */ 40 41 #ifdef CONFIG_MCF5301x 42 #define FREF 20000 /* KHz */ 43 #define MAX_MFD 63 /* Multiplier */ 44 #define MIN_MFD 0 /* Multiplier */ 45 #define USBDIV 8 46 47 /* Low Power Divider specifications */ 48 #define MIN_LPD (0) /* Divider (not encoded) */ 49 #define MAX_LPD (15) /* Divider (not encoded) */ 50 #define DEFAULT_LPD (0) /* Divider (not encoded) */ 51 #endif 52 53 #ifdef CONFIG_MCF532x 54 #define FREF 16000 /* KHz */ 55 #define MAX_MFD 135 /* Multiplier */ 56 #define MIN_MFD 88 /* Multiplier */ 57 58 /* Low Power Divider specifications */ 59 #define MIN_LPD (1 << 0) /* Divider (not encoded) */ 60 #define MAX_LPD (1 << 15) /* Divider (not encoded) */ 61 #define DEFAULT_LPD (1 << 1) /* Divider (not encoded) */ 62 #endif 63 64 #define BUSDIV 6 /* Divider */ 65 66 /* Get the value of the current system clock */ 67 int get_sys_clock(void) 68 { 69 ccm_t *ccm = (ccm_t *)(MMAP_CCM); 70 pll_t *pll = (pll_t *)(MMAP_PLL); 71 int divider; 72 73 /* Test to see if device is in LIMP mode */ 74 if (in_be16(&ccm->misccr) & CCM_MISCCR_LIMP) { 75 divider = in_be16(&ccm->cdr) & CCM_CDR_LPDIV(0xF); 76 #ifdef CONFIG_MCF5301x 77 return (FREF / (3 * (1 << divider))); 78 #endif 79 #ifdef CONFIG_MCF532x 80 return (FREF / (2 << divider)); 81 #endif 82 } else { 83 #ifdef CONFIG_MCF5301x 84 u32 pfdr = (in_be32(&pll->pcr) & 0x3F) + 1; 85 u32 refdiv = (1 << ((in_be32(&pll->pcr) & PLL_PCR_REFDIV(7)) >> 8)); 86 u32 busdiv = ((in_be32(&pll->pdr) & 0x00F0) >> 4) + 1; 87 88 return (((FREF * pfdr) / refdiv) / busdiv); 89 #endif 90 #ifdef CONFIG_MCF532x 91 return (FREF * in_8(&pll->pfdr)) / (BUSDIV * 4); 92 #endif 93 } 94 } 95 96 /* 97 * Initialize the Low Power Divider circuit 98 * 99 * Parameters: 100 * div Desired system frequency divider 101 * 102 * Return Value: 103 * The resulting output system frequency 104 */ 105 int clock_limp(int div) 106 { 107 ccm_t *ccm = (ccm_t *)(MMAP_CCM); 108 u32 temp; 109 110 /* Check bounds of divider */ 111 if (div < MIN_LPD) 112 div = MIN_LPD; 113 if (div > MAX_LPD) 114 div = MAX_LPD; 115 116 /* Save of the current value of the SSIDIV so we don't overwrite the value */ 117 temp = (in_be16(&ccm->cdr) & CCM_CDR_SSIDIV(0xFF)); 118 119 /* Apply the divider to the system clock */ 120 out_be16(&ccm->cdr, CCM_CDR_LPDIV(div) | CCM_CDR_SSIDIV(temp)); 121 122 setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); 123 124 return (FREF / (3 * (1 << div))); 125 } 126 127 /* Exit low power LIMP mode */ 128 int clock_exit_limp(void) 129 { 130 ccm_t *ccm = (ccm_t *)(MMAP_CCM); 131 int fout; 132 133 /* Exit LIMP mode */ 134 clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); 135 136 /* Wait for PLL to lock */ 137 while (!(in_be16(&ccm->misccr) & CCM_MISCCR_PLL_LOCK)) 138 ; 139 140 fout = get_sys_clock(); 141 142 return fout; 143 } 144 145 /* Initialize the PLL 146 * 147 * Parameters: 148 * fref PLL reference clock frequency in KHz 149 * fsys Desired PLL output frequency in KHz 150 * flags Operating parameters 151 * 152 * Return Value: 153 * The resulting output system frequency 154 */ 155 int clock_pll(int fsys, int flags) 156 { 157 #ifdef CONFIG_MCF532x 158 u32 *sdram_workaround = (u32 *)(MMAP_SDRAM + 0x80); 159 #endif 160 sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); 161 pll_t *pll = (pll_t *)(MMAP_PLL); 162 int fref, temp, fout, mfd; 163 u32 i; 164 165 fref = FREF; 166 167 if (fsys == 0) { 168 /* Return current PLL output */ 169 #ifdef CONFIG_MCF5301x 170 u32 busdiv = ((in_be32(&pll->pdr) >> 4) & 0x0F) + 1; 171 mfd = (in_be32(&pll->pcr) & 0x3F) + 1; 172 173 return (fref * mfd) / busdiv; 174 #endif 175 #ifdef CONFIG_MCF532x 176 mfd = in_8(&pll->pfdr); 177 178 return (fref * mfd / (BUSDIV * 4)); 179 #endif 180 } 181 182 /* Check bounds of requested system clock */ 183 if (fsys > MAX_FSYS) 184 fsys = MAX_FSYS; 185 186 if (fsys < MIN_FSYS) 187 fsys = MIN_FSYS; 188 189 /* 190 * Multiplying by 100 when calculating the temp value, 191 * and then dividing by 100 to calculate the mfd allows 192 * for exact values without needing to include floating 193 * point libraries. 194 */ 195 temp = (100 * fsys) / fref; 196 #ifdef CONFIG_MCF5301x 197 mfd = (BUSDIV * temp) / 100; 198 199 /* Determine the output frequency for selected values */ 200 fout = ((fref * mfd) / BUSDIV); 201 #endif 202 #ifdef CONFIG_MCF532x 203 mfd = (4 * BUSDIV * temp) / 100; 204 205 /* Determine the output frequency for selected values */ 206 fout = ((fref * mfd) / (BUSDIV * 4)); 207 #endif 208 209 /* must not tamper with SDRAMC if running from SDRAM */ 210 #if !defined(CONFIG_MONITOR_IS_IN_RAM) 211 /* 212 * Check to see if the SDRAM has already been initialized. 213 * If it has then the SDRAM needs to be put into self refresh 214 * mode before reprogramming the PLL. 215 */ 216 if (in_be32(&sdram->ctrl) & SDRAMC_SDCR_REF) 217 clrbits_be32(&sdram->ctrl, SDRAMC_SDCR_CKE); 218 219 /* 220 * Initialize the PLL to generate the new system clock frequency. 221 * The device must be put into LIMP mode to reprogram the PLL. 222 */ 223 224 /* Enter LIMP mode */ 225 clock_limp(DEFAULT_LPD); 226 227 #ifdef CONFIG_MCF5301x 228 out_be32(&pll->pdr, 229 PLL_PDR_OUTDIV1((BUSDIV / 3) - 1) | 230 PLL_PDR_OUTDIV2(BUSDIV - 1) | 231 PLL_PDR_OUTDIV3((BUSDIV / 2) - 1) | 232 PLL_PDR_OUTDIV4(USBDIV - 1)); 233 234 clrbits_be32(&pll->pcr, ~PLL_PCR_FBDIV_UNMASK); 235 setbits_be32(&pll->pcr, PLL_PCR_FBDIV(mfd - 1)); 236 #endif 237 #ifdef CONFIG_MCF532x 238 /* Reprogram PLL for desired fsys */ 239 out_8(&pll->podr, 240 PLL_PODR_CPUDIV(BUSDIV / 3) | PLL_PODR_BUSDIV(BUSDIV)); 241 242 out_8(&pll->pfdr, mfd); 243 #endif 244 245 /* Exit LIMP mode */ 246 clock_exit_limp(); 247 248 /* Return the SDRAM to normal operation if it is in use. */ 249 if (in_be32(&sdram->ctrl) & SDRAMC_SDCR_REF) 250 setbits_be32(&sdram->ctrl, SDRAMC_SDCR_CKE); 251 252 #ifdef CONFIG_MCF532x 253 /* 254 * software workaround for SDRAM opeartion after exiting LIMP 255 * mode errata 256 */ 257 out_be32(sdram_workaround, CONFIG_SYS_SDRAM_BASE); 258 #endif 259 260 /* wait for DQS logic to relock */ 261 for (i = 0; i < 0x200; i++) ; 262 #endif /* !defined(CONFIG_MONITOR_IS_IN_RAM) */ 263 264 return fout; 265 } 266 267 /* get_clocks() fills in gd->cpu_clock and gd->bus_clk */ 268 int get_clocks(void) 269 { 270 gd->bus_clk = clock_pll(CONFIG_SYS_CLK / 1000, 0) * 1000; 271 gd->cpu_clk = (gd->bus_clk * 3); 272 273 #ifdef CONFIG_FSL_I2C 274 gd->arch.i2c1_clk = gd->bus_clk; 275 #endif 276 277 return (0); 278 } 279