1 /* 2 * 3 * (C) Copyright 2000-2003 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 * 6 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #include <common.h> 29 #include <asm/processor.h> 30 31 #include <asm/immap.h> 32 33 DECLARE_GLOBAL_DATA_PTR; 34 35 /* PLL min/max specifications */ 36 #define MAX_FVCO 500000 /* KHz */ 37 #define MAX_FSYS 80000 /* KHz */ 38 #define MIN_FSYS 58333 /* KHz */ 39 40 #ifdef CONFIG_MCF5301x 41 #define FREF 20000 /* KHz */ 42 #define MAX_MFD 63 /* Multiplier */ 43 #define MIN_MFD 0 /* Multiplier */ 44 #define USBDIV 8 45 46 /* Low Power Divider specifications */ 47 #define MIN_LPD (0) /* Divider (not encoded) */ 48 #define MAX_LPD (15) /* Divider (not encoded) */ 49 #define DEFAULT_LPD (0) /* Divider (not encoded) */ 50 #endif 51 52 #ifdef CONFIG_MCF532x 53 #define FREF 16000 /* KHz */ 54 #define MAX_MFD 135 /* Multiplier */ 55 #define MIN_MFD 88 /* Multiplier */ 56 57 /* Low Power Divider specifications */ 58 #define MIN_LPD (1 << 0) /* Divider (not encoded) */ 59 #define MAX_LPD (1 << 15) /* Divider (not encoded) */ 60 #define DEFAULT_LPD (1 << 1) /* Divider (not encoded) */ 61 #endif 62 63 #define BUSDIV 6 /* Divider */ 64 65 /* Get the value of the current system clock */ 66 int get_sys_clock(void) 67 { 68 volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM); 69 volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL); 70 int divider; 71 72 /* Test to see if device is in LIMP mode */ 73 if (ccm->misccr & CCM_MISCCR_LIMP) { 74 divider = ccm->cdr & CCM_CDR_LPDIV(0xF); 75 #ifdef CONFIG_MCF5301x 76 return (FREF / (3 * (1 << divider))); 77 #endif 78 #ifdef CONFIG_MCF532x 79 return (FREF / (2 << divider)); 80 #endif 81 } else { 82 #ifdef CONFIG_MCF5301x 83 u32 pfdr = (pll->pcr & 0x3F) + 1; 84 u32 refdiv = (1 << ((pll->pcr & PLL_PCR_REFDIV(7)) >> 8)); 85 u32 busdiv = ((pll->pdr & 0x00F0) >> 4) + 1; 86 87 return (((FREF * pfdr) / refdiv) / busdiv); 88 #endif 89 #ifdef CONFIG_MCF532x 90 return ((FREF * pll->pfdr) / (BUSDIV * 4)); 91 #endif 92 } 93 } 94 95 /* 96 * Initialize the Low Power Divider circuit 97 * 98 * Parameters: 99 * div Desired system frequency divider 100 * 101 * Return Value: 102 * The resulting output system frequency 103 */ 104 int clock_limp(int div) 105 { 106 volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM); 107 u32 temp; 108 109 /* Check bounds of divider */ 110 if (div < MIN_LPD) 111 div = MIN_LPD; 112 if (div > MAX_LPD) 113 div = MAX_LPD; 114 115 /* Save of the current value of the SSIDIV so we don't overwrite the value */ 116 temp = (ccm->cdr & CCM_CDR_SSIDIV(0xFF)); 117 118 /* Apply the divider to the system clock */ 119 ccm->cdr = (CCM_CDR_LPDIV(div) | CCM_CDR_SSIDIV(temp)); 120 121 ccm->misccr |= CCM_MISCCR_LIMP; 122 123 return (FREF / (3 * (1 << div))); 124 } 125 126 /* Exit low power LIMP mode */ 127 int clock_exit_limp(void) 128 { 129 volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM); 130 int fout; 131 132 /* Exit LIMP mode */ 133 ccm->misccr &= (~CCM_MISCCR_LIMP); 134 135 /* Wait for PLL to lock */ 136 while (!(ccm->misccr & CCM_MISCCR_PLL_LOCK)) ; 137 138 fout = get_sys_clock(); 139 140 return fout; 141 } 142 143 /* Initialize the PLL 144 * 145 * Parameters: 146 * fref PLL reference clock frequency in KHz 147 * fsys Desired PLL output frequency in KHz 148 * flags Operating parameters 149 * 150 * Return Value: 151 * The resulting output system frequency 152 */ 153 int clock_pll(int fsys, int flags) 154 { 155 #ifdef CONFIG_MCF532x 156 volatile u32 *sdram_workaround = (volatile u32 *)(MMAP_SDRAM + 0x80); 157 #endif 158 volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM); 159 volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL); 160 int fref, temp, fout, mfd; 161 u32 i; 162 163 fref = FREF; 164 165 if (fsys == 0) { 166 /* Return current PLL output */ 167 #ifdef CONFIG_MCF5301x 168 u32 busdiv = ((pll->pdr >> 4) & 0x0F) + 1; 169 mfd = (pll->pcr & 0x3F) + 1; 170 171 return (fref * mfd) / busdiv; 172 #endif 173 #ifdef CONFIG_MCF532x 174 mfd = pll->pfdr; 175 176 return (fref * mfd / (BUSDIV * 4)); 177 #endif 178 } 179 180 /* Check bounds of requested system clock */ 181 if (fsys > MAX_FSYS) 182 fsys = MAX_FSYS; 183 184 if (fsys < MIN_FSYS) 185 fsys = MIN_FSYS; 186 187 /* 188 * Multiplying by 100 when calculating the temp value, 189 * and then dividing by 100 to calculate the mfd allows 190 * for exact values without needing to include floating 191 * point libraries. 192 */ 193 temp = (100 * fsys) / fref; 194 #ifdef CONFIG_MCF5301x 195 mfd = (BUSDIV * temp) / 100; 196 197 /* Determine the output frequency for selected values */ 198 fout = ((fref * mfd) / BUSDIV); 199 #endif 200 #ifdef CONFIG_MCF532x 201 mfd = (4 * BUSDIV * temp) / 100; 202 203 /* Determine the output frequency for selected values */ 204 fout = ((fref * mfd) / (BUSDIV * 4)); 205 #endif 206 207 /* must not tamper with SDRAMC if running from SDRAM */ 208 #if !defined(CONFIG_MONITOR_IS_IN_RAM) 209 /* 210 * Check to see if the SDRAM has already been initialized. 211 * If it has then the SDRAM needs to be put into self refresh 212 * mode before reprogramming the PLL. 213 */ 214 if (sdram->ctrl & SDRAMC_SDCR_REF) 215 sdram->ctrl &= ~SDRAMC_SDCR_CKE; 216 217 /* 218 * Initialize the PLL to generate the new system clock frequency. 219 * The device must be put into LIMP mode to reprogram the PLL. 220 */ 221 222 /* Enter LIMP mode */ 223 clock_limp(DEFAULT_LPD); 224 225 #ifdef CONFIG_MCF5301x 226 pll->pdr = 227 PLL_PDR_OUTDIV1((BUSDIV / 3) - 1) | 228 PLL_PDR_OUTDIV2(BUSDIV - 1) | 229 PLL_PDR_OUTDIV3((BUSDIV / 2) - 1) | 230 PLL_PDR_OUTDIV4(USBDIV - 1); 231 232 pll->pcr &= PLL_PCR_FBDIV_UNMASK; 233 pll->pcr |= PLL_PCR_FBDIV(mfd - 1); 234 #endif 235 #ifdef CONFIG_MCF532x 236 /* Reprogram PLL for desired fsys */ 237 pll->podr = (PLL_PODR_CPUDIV(BUSDIV / 3) | PLL_PODR_BUSDIV(BUSDIV)); 238 239 pll->pfdr = mfd; 240 #endif 241 242 /* Exit LIMP mode */ 243 clock_exit_limp(); 244 245 /* Return the SDRAM to normal operation if it is in use. */ 246 if (sdram->ctrl & SDRAMC_SDCR_REF) 247 sdram->ctrl |= SDRAMC_SDCR_CKE; 248 249 #ifdef CONFIG_MCF532x 250 /* 251 * software workaround for SDRAM opeartion after exiting LIMP 252 * mode errata 253 */ 254 *sdram_workaround = CONFIG_SYS_SDRAM_BASE; 255 #endif 256 257 /* wait for DQS logic to relock */ 258 for (i = 0; i < 0x200; i++) ; 259 #endif /* !defined(CONFIG_MONITOR_IS_IN_RAM) */ 260 261 return fout; 262 } 263 264 /* get_clocks() fills in gd->cpu_clock and gd->bus_clk */ 265 int get_clocks(void) 266 { 267 gd->bus_clk = clock_pll(CONFIG_SYS_CLK / 1000, 0) * 1000; 268 gd->cpu_clk = (gd->bus_clk * 3); 269 270 #ifdef CONFIG_FSL_I2C 271 gd->i2c1_clk = gd->bus_clk; 272 #endif 273 274 return (0); 275 } 276