1 /* 2 * 3 * (C) Copyright 2000-2003 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 * 6 * (C) Copyright 2004-2008, 2012 Freescale Semiconductor, Inc. 7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #include <common.h> 29 #include <watchdog.h> 30 #include <asm/immap.h> 31 #include <asm/io.h> 32 33 #if defined(CONFIG_CMD_NET) 34 #include <config.h> 35 #include <net.h> 36 #include <asm/fec.h> 37 #endif 38 39 #ifdef CONFIG_MCF5301x 40 void cpu_init_f(void) 41 { 42 scm1_t *scm1 = (scm1_t *) MMAP_SCM1; 43 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 44 fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; 45 46 out_be32(&scm1->mpr, 0x77777777); 47 out_be32(&scm1->pacra, 0); 48 out_be32(&scm1->pacrb, 0); 49 out_be32(&scm1->pacrc, 0); 50 out_be32(&scm1->pacrd, 0); 51 out_be32(&scm1->pacre, 0); 52 out_be32(&scm1->pacrf, 0); 53 out_be32(&scm1->pacrg, 0); 54 55 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ 56 && defined(CONFIG_SYS_CS0_CTRL)) 57 setbits_8(&gpio->par_cs, GPIO_PAR_CS0_CS0); 58 out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); 59 out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); 60 out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); 61 #endif 62 63 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ 64 && defined(CONFIG_SYS_CS1_CTRL)) 65 setbits_8(&gpio->par_cs, GPIO_PAR_CS1_CS1); 66 out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); 67 out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); 68 out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); 69 #endif 70 71 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ 72 && defined(CONFIG_SYS_CS2_CTRL)) 73 out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); 74 out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); 75 out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); 76 #endif 77 78 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ 79 && defined(CONFIG_SYS_CS3_CTRL)) 80 out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); 81 out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); 82 out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); 83 #endif 84 85 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ 86 && defined(CONFIG_SYS_CS4_CTRL)) 87 setbits_8(&gpio->par_cs, GPIO_PAR_CS4); 88 out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE); 89 out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL); 90 out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK); 91 #endif 92 93 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \ 94 && defined(CONFIG_SYS_CS5_CTRL)) 95 setbits_8(&gpio->par_cs, GPIO_PAR_CS5); 96 out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE); 97 out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL); 98 out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK); 99 #endif 100 101 #ifdef CONFIG_FSL_I2C 102 out_8(&gpio->par_feci2c, 103 GPIO_PAR_FECI2C_SDA_SDA | GPIO_PAR_FECI2C_SCL_SCL); 104 #endif 105 106 icache_enable(); 107 } 108 109 /* initialize higher level parts of CPU like timers */ 110 int cpu_init_r(void) 111 { 112 #ifdef CONFIG_MCFFEC 113 ccm_t *ccm = (ccm_t *) MMAP_CCM; 114 #endif 115 #ifdef CONFIG_MCFRTC 116 rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE); 117 rtcex_t *rtcex = (rtcex_t *) &rtc->extended; 118 119 out_be32(&rtcex->gocu, CONFIG_SYS_RTC_CNT); 120 out_be32(&rtcex->gocl, CONFIG_SYS_RTC_SETUP); 121 122 #endif 123 #ifdef CONFIG_MCFFEC 124 if (CONFIG_SYS_FEC0_MIIBASE != CONFIG_SYS_FEC1_MIIBASE) 125 setbits_be16(&ccm->misccr, CCM_MISCCR_FECM); 126 else 127 clrbits_be16(&ccm->misccr, CCM_MISCCR_FECM); 128 #endif 129 130 return (0); 131 } 132 133 void uart_port_conf(int port) 134 { 135 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 136 137 /* Setup Ports: */ 138 switch (port) { 139 case 0: 140 clrbits_8(&gpio->par_uart, 141 GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD); 142 setbits_8(&gpio->par_uart, 143 GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD); 144 break; 145 case 1: 146 #ifdef CONFIG_SYS_UART1_ALT1_GPIO 147 clrbits_8(&gpio->par_simp1h, 148 GPIO_PAR_SIMP1H_DATA1_UNMASK | 149 GPIO_PAR_SIMP1H_VEN1_UNMASK); 150 setbits_8(&gpio->par_simp1h, 151 GPIO_PAR_SIMP1H_DATA1_U1TXD | 152 GPIO_PAR_SIMP1H_VEN1_U1RXD); 153 #elif defined(CONFIG_SYS_UART1_ALT2_GPIO) 154 clrbits_8(&gpio->par_ssih, 155 GPIO_PAR_SSIH_RXD_UNMASK | 156 GPIO_PAR_SSIH_TXD_UNMASK); 157 setbits_8(&gpio->par_ssih, 158 GPIO_PAR_SSIH_RXD_U1RXD | 159 GPIO_PAR_SSIH_TXD_U1TXD); 160 #endif 161 break; 162 case 2: 163 #ifdef CONFIG_SYS_UART2_PRI_GPIO 164 setbits_8(&gpio->par_uart, 165 GPIO_PAR_UART_U2TXD | 166 GPIO_PAR_UART_U2RXD); 167 #elif defined(CONFIG_SYS_UART2_ALT1_GPIO) 168 clrbits_8(&gpio->par_dspih, 169 GPIO_PAR_DSPIH_SIN_UNMASK | 170 GPIO_PAR_DSPIH_SOUT_UNMASK); 171 setbits_8(&gpio->par_dspih, 172 GPIO_PAR_DSPIH_SIN_U2RXD | 173 GPIO_PAR_DSPIH_SOUT_U2TXD); 174 #elif defined(CONFIG_SYS_UART2_ALT2_GPIO) 175 clrbits_8(&gpio->par_feci2c, 176 GPIO_PAR_FECI2C_SDA_UNMASK | 177 GPIO_PAR_FECI2C_SCL_UNMASK); 178 setbits_8(&gpio->par_feci2c, 179 GPIO_PAR_FECI2C_SDA_U2TXD | 180 GPIO_PAR_FECI2C_SCL_U2RXD); 181 #endif 182 break; 183 } 184 } 185 186 #if defined(CONFIG_CMD_NET) 187 int fecpin_setclear(struct eth_device *dev, int setclear) 188 { 189 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 190 struct fec_info_s *info = (struct fec_info_s *)dev->priv; 191 192 if (setclear) { 193 if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { 194 setbits_8(&gpio->par_fec, 195 GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC); 196 setbits_8(&gpio->par_feci2c, 197 GPIO_PAR_FECI2C_MDC0 | GPIO_PAR_FECI2C_MDIO0); 198 } else { 199 setbits_8(&gpio->par_fec, 200 GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC); 201 setbits_8(&gpio->par_feci2c, 202 GPIO_PAR_FECI2C_MDC1 | GPIO_PAR_FECI2C_MDIO1); 203 } 204 } else { 205 if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { 206 clrbits_8(&gpio->par_fec, 207 GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC); 208 clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII0_UNMASK); 209 } else { 210 clrbits_8(&gpio->par_fec, 211 GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC); 212 clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII1_UNMASK); 213 } 214 } 215 return 0; 216 } 217 #endif /* CONFIG_CMD_NET */ 218 #endif /* CONFIG_MCF5301x */ 219 220 #ifdef CONFIG_MCF532x 221 void cpu_init_f(void) 222 { 223 scm1_t *scm1 = (scm1_t *) MMAP_SCM1; 224 scm2_t *scm2 = (scm2_t *) MMAP_SCM2; 225 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 226 fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; 227 wdog_t *wdog = (wdog_t *) MMAP_WDOG; 228 229 /* watchdog is enabled by default - disable the watchdog */ 230 #ifndef CONFIG_WATCHDOG 231 out_be16(&wdog->cr, 0); 232 #endif 233 234 out_be32(&scm1->mpr0, 0x77777777); 235 out_be32(&scm2->pacra, 0); 236 out_be32(&scm2->pacrb, 0); 237 out_be32(&scm2->pacrc, 0); 238 out_be32(&scm2->pacrd, 0); 239 out_be32(&scm2->pacre, 0); 240 out_be32(&scm2->pacrf, 0); 241 out_be32(&scm2->pacrg, 0); 242 out_be32(&scm1->pacrh, 0); 243 244 /* Port configuration */ 245 out_8(&gpio->par_cs, 0); 246 247 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ 248 && defined(CONFIG_SYS_CS0_CTRL)) 249 out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); 250 out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); 251 out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); 252 #endif 253 254 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ 255 && defined(CONFIG_SYS_CS1_CTRL)) 256 /* Latch chipselect */ 257 setbits_8(&gpio->par_cs, GPIO_PAR_CS1); 258 out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); 259 out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); 260 out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); 261 #endif 262 263 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ 264 && defined(CONFIG_SYS_CS2_CTRL)) 265 setbits_8(&gpio->par_cs, GPIO_PAR_CS2); 266 out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); 267 out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); 268 out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); 269 #endif 270 271 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ 272 && defined(CONFIG_SYS_CS3_CTRL)) 273 setbits_8(&gpio->par_cs, GPIO_PAR_CS3); 274 out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); 275 out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); 276 out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); 277 #endif 278 279 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ 280 && defined(CONFIG_SYS_CS4_CTRL)) 281 setbits_8(&gpio->par_cs, GPIO_PAR_CS4); 282 out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE); 283 out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL); 284 out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK); 285 #endif 286 287 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \ 288 && defined(CONFIG_SYS_CS5_CTRL)) 289 setbits_8(&gpio->par_cs, GPIO_PAR_CS5); 290 out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE); 291 out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL); 292 out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK); 293 #endif 294 295 #ifdef CONFIG_FSL_I2C 296 out_8(&gpio->par_feci2c, 297 GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA); 298 #endif 299 300 icache_enable(); 301 } 302 303 /* 304 * initialize higher level parts of CPU like timers 305 */ 306 int cpu_init_r(void) 307 { 308 return (0); 309 } 310 311 void uart_port_conf(int port) 312 { 313 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 314 315 /* Setup Ports: */ 316 switch (port) { 317 case 0: 318 clrbits_be16(&gpio->par_uart, 319 GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0); 320 setbits_be16(&gpio->par_uart, 321 GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0); 322 break; 323 case 1: 324 clrbits_be16(&gpio->par_uart, 325 GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3)); 326 setbits_be16(&gpio->par_uart, 327 GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3)); 328 break; 329 case 2: 330 #ifdef CONFIG_SYS_UART2_ALT1_GPIO 331 clrbits_8(&gpio->par_timer, 0xf0); 332 setbits_8(&gpio->par_timer, 333 GPIO_PAR_TIN3_URXD2 | GPIO_PAR_TIN2_UTXD2); 334 #elif defined(CONFIG_SYS_UART2_ALT2_GPIO) 335 clrbits_8(&gpio->par_feci2c, 0x00ff); 336 setbits_8(&gpio->par_feci2c, 337 GPIO_PAR_FECI2C_SCL_UTXD2 | GPIO_PAR_FECI2C_SDA_URXD2); 338 #elif defined(CONFIG_SYS_UART2_ALT3_GPIO) 339 clrbits_be16(&gpio->par_ssi, 0x0f00); 340 setbits_be16(&gpio->par_ssi, 341 GPIO_PAR_SSI_RXD(2) | GPIO_PAR_SSI_TXD(2)); 342 #endif 343 break; 344 } 345 } 346 347 #if defined(CONFIG_CMD_NET) 348 int fecpin_setclear(struct eth_device *dev, int setclear) 349 { 350 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 351 352 if (setclear) { 353 setbits_8(&gpio->par_fec, 354 GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC); 355 setbits_8(&gpio->par_feci2c, 356 GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO); 357 } else { 358 clrbits_8(&gpio->par_fec, 359 GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC); 360 clrbits_8(&gpio->par_feci2c, 361 GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO); 362 } 363 return 0; 364 } 365 #endif 366 #endif /* CONFIG_MCF532x */ 367