1 /* 2 * 3 * (C) Copyright 2000-2003 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 * 6 * (C) Copyright 2004-2008 Freescale Semiconductor, Inc. 7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #include <common.h> 29 #include <watchdog.h> 30 #include <asm/immap.h> 31 32 #if defined(CONFIG_CMD_NET) 33 #include <config.h> 34 #include <net.h> 35 #include <asm/fec.h> 36 #endif 37 38 #ifdef CONFIG_MCF5301x 39 void cpu_init_f(void) 40 { 41 volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1; 42 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; 43 volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; 44 45 /* watchdog is enabled by default - disable the watchdog */ 46 #ifndef CONFIG_WATCHDOG 47 /*wdog->cr = 0; */ 48 #endif 49 50 scm1->mpr = 0x77777777; 51 scm1->pacra = 0; 52 scm1->pacrb = 0; 53 scm1->pacrc = 0; 54 scm1->pacrd = 0; 55 scm1->pacre = 0; 56 scm1->pacrf = 0; 57 scm1->pacrg = 0; 58 59 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ 60 && defined(CONFIG_SYS_CS0_CTRL)) 61 gpio->par_cs |= GPIO_PAR_CS0_CS0; 62 fbcs->csar0 = CONFIG_SYS_CS0_BASE; 63 fbcs->cscr0 = CONFIG_SYS_CS0_CTRL; 64 fbcs->csmr0 = CONFIG_SYS_CS0_MASK; 65 #endif 66 67 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ 68 && defined(CONFIG_SYS_CS1_CTRL)) 69 gpio->par_cs |= GPIO_PAR_CS1_CS1; 70 fbcs->csar1 = CONFIG_SYS_CS1_BASE; 71 fbcs->cscr1 = CONFIG_SYS_CS1_CTRL; 72 fbcs->csmr1 = CONFIG_SYS_CS1_MASK; 73 #endif 74 75 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ 76 && defined(CONFIG_SYS_CS2_CTRL)) 77 fbcs->csar2 = CONFIG_SYS_CS2_BASE; 78 fbcs->cscr2 = CONFIG_SYS_CS2_CTRL; 79 fbcs->csmr2 = CONFIG_SYS_CS2_MASK; 80 #endif 81 82 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ 83 && defined(CONFIG_SYS_CS3_CTRL)) 84 fbcs->csar3 = CONFIG_SYS_CS3_BASE; 85 fbcs->cscr3 = CONFIG_SYS_CS3_CTRL; 86 fbcs->csmr3 = CONFIG_SYS_CS3_MASK; 87 #endif 88 89 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ 90 && defined(CONFIG_SYS_CS4_CTRL)) 91 gpio->par_cs |= GPIO_PAR_CS4; 92 fbcs->csar4 = CONFIG_SYS_CS4_BASE; 93 fbcs->cscr4 = CONFIG_SYS_CS4_CTRL; 94 fbcs->csmr4 = CONFIG_SYS_CS4_MASK; 95 #endif 96 97 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \ 98 && defined(CONFIG_SYS_CS5_CTRL)) 99 gpio->par_cs |= GPIO_PAR_CS5; 100 fbcs->csar5 = CONFIG_SYS_CS5_BASE; 101 fbcs->cscr5 = CONFIG_SYS_CS5_CTRL; 102 fbcs->csmr5 = CONFIG_SYS_CS5_MASK; 103 #endif 104 105 #ifdef CONFIG_FSL_I2C 106 gpio->par_feci2c = GPIO_PAR_FECI2C_SDA_SDA | GPIO_PAR_FECI2C_SCL_SCL; 107 #endif 108 109 icache_enable(); 110 } 111 112 /* initialize higher level parts of CPU like timers */ 113 int cpu_init_r(void) 114 { 115 #ifdef CONFIG_MCFFEC 116 volatile ccm_t *ccm = (ccm_t *) MMAP_CCM; 117 #endif 118 #ifdef CONFIG_MCFRTC 119 volatile rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE); 120 volatile rtcex_t *rtcex = (rtcex_t *) & rtc->extended; 121 122 rtcex->gocu = CONFIG_SYS_RTC_CNT; 123 rtcex->gocl = CONFIG_SYS_RTC_SETUP; 124 125 #endif 126 #ifdef CONFIG_MCFFEC 127 if (CONFIG_SYS_FEC0_MIIBASE != CONFIG_SYS_FEC1_MIIBASE) 128 ccm->misccr |= CCM_MISCCR_FECM; 129 else 130 ccm->misccr &= ~CCM_MISCCR_FECM; 131 #endif 132 133 return (0); 134 } 135 136 void uart_port_conf(int port) 137 { 138 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; 139 140 /* Setup Ports: */ 141 switch (port) { 142 case 0: 143 gpio->par_uart &= ~(GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD); 144 gpio->par_uart |= (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD); 145 break; 146 case 1: 147 #ifdef CONFIG_SYS_UART1_ALT1_GPIO 148 gpio->par_simp1h &= 149 ~(GPIO_PAR_SIMP1H_DATA1_UNMASK | 150 GPIO_PAR_SIMP1H_VEN1_UNMASK); 151 gpio->par_simp1h |= 152 (GPIO_PAR_SIMP1H_DATA1_U1TXD | GPIO_PAR_SIMP1H_VEN1_U1RXD); 153 #elif defined(CONFIG_SYS_UART1_ALT2_GPIO) 154 gpio->par_ssih &= 155 ~(GPIO_PAR_SSIH_RXD_UNMASK | GPIO_PAR_SSIH_TXD_UNMASK); 156 gpio->par_ssih |= 157 (GPIO_PAR_SSIH_RXD_U1RXD | GPIO_PAR_SSIH_TXD_U1TXD); 158 #endif 159 break; 160 case 2: 161 #ifdef CONFIG_SYS_UART2_PRI_GPIO 162 gpio->par_uart |= (GPIO_PAR_UART_U2TXD | GPIO_PAR_UART_U2RXD); 163 #elif defined(CONFIG_SYS_UART2_ALT1_GPIO) 164 gpio->par_dspih &= 165 ~(GPIO_PAR_DSPIH_SIN_UNMASK | GPIO_PAR_DSPIH_SOUT_UNMASK); 166 gpio->par_dspih |= 167 (GPIO_PAR_DSPIH_SIN_U2RXD | GPIO_PAR_DSPIH_SOUT_U2TXD); 168 #elif defined(CONFIG_SYS_UART2_ALT2_GPIO) 169 gpio->par_feci2c &= 170 ~(GPIO_PAR_FECI2C_SDA_UNMASK | GPIO_PAR_FECI2C_SCL_UNMASK); 171 gpio->par_feci2c |= 172 (GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD); 173 #endif 174 break; 175 } 176 } 177 178 #if defined(CONFIG_CMD_NET) 179 int fecpin_setclear(struct eth_device *dev, int setclear) 180 { 181 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; 182 struct fec_info_s *info = (struct fec_info_s *)dev->priv; 183 184 if (setclear) { 185 if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { 186 gpio->par_fec |= 187 GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC; 188 gpio->par_feci2c |= 189 GPIO_PAR_FECI2C_MDC0 | GPIO_PAR_FECI2C_MDIO0; 190 } else { 191 gpio->par_fec |= 192 GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC; 193 gpio->par_feci2c |= 194 GPIO_PAR_FECI2C_MDC1 | GPIO_PAR_FECI2C_MDIO1; 195 } 196 } else { 197 if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { 198 gpio->par_fec &= 199 ~(GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC); 200 gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII0_UNMASK; 201 } else { 202 gpio->par_fec &= 203 ~(GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC); 204 gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII1_UNMASK; 205 } 206 } 207 return 0; 208 } 209 #endif /* CONFIG_CMD_NET */ 210 #endif /* CONFIG_MCF5301x */ 211 212 #ifdef CONFIG_MCF532x 213 void cpu_init_f(void) 214 { 215 volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1; 216 volatile scm2_t *scm2 = (scm2_t *) MMAP_SCM2; 217 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; 218 volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; 219 volatile wdog_t *wdog = (wdog_t *) MMAP_WDOG; 220 221 /* watchdog is enabled by default - disable the watchdog */ 222 #ifndef CONFIG_WATCHDOG 223 wdog->cr = 0; 224 #endif 225 226 scm1->mpr0 = 0x77777777; 227 scm2->pacra = 0; 228 scm2->pacrb = 0; 229 scm2->pacrc = 0; 230 scm2->pacrd = 0; 231 scm2->pacre = 0; 232 scm2->pacrf = 0; 233 scm2->pacrg = 0; 234 scm1->pacrh = 0; 235 236 /* Port configuration */ 237 gpio->par_cs = 0; 238 239 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ 240 && defined(CONFIG_SYS_CS0_CTRL)) 241 fbcs->csar0 = CONFIG_SYS_CS0_BASE; 242 fbcs->cscr0 = CONFIG_SYS_CS0_CTRL; 243 fbcs->csmr0 = CONFIG_SYS_CS0_MASK; 244 #endif 245 246 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ 247 && defined(CONFIG_SYS_CS1_CTRL)) 248 /* Latch chipselect */ 249 gpio->par_cs |= GPIO_PAR_CS1; 250 fbcs->csar1 = CONFIG_SYS_CS1_BASE; 251 fbcs->cscr1 = CONFIG_SYS_CS1_CTRL; 252 fbcs->csmr1 = CONFIG_SYS_CS1_MASK; 253 #endif 254 255 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ 256 && defined(CONFIG_SYS_CS2_CTRL)) 257 gpio->par_cs |= GPIO_PAR_CS2; 258 fbcs->csar2 = CONFIG_SYS_CS2_BASE; 259 fbcs->cscr2 = CONFIG_SYS_CS2_CTRL; 260 fbcs->csmr2 = CONFIG_SYS_CS2_MASK; 261 #endif 262 263 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ 264 && defined(CONFIG_SYS_CS3_CTRL)) 265 gpio->par_cs |= GPIO_PAR_CS3; 266 fbcs->csar3 = CONFIG_SYS_CS3_BASE; 267 fbcs->cscr3 = CONFIG_SYS_CS3_CTRL; 268 fbcs->csmr3 = CONFIG_SYS_CS3_MASK; 269 #endif 270 271 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ 272 && defined(CONFIG_SYS_CS4_CTRL)) 273 gpio->par_cs |= GPIO_PAR_CS4; 274 fbcs->csar4 = CONFIG_SYS_CS4_BASE; 275 fbcs->cscr4 = CONFIG_SYS_CS4_CTRL; 276 fbcs->csmr4 = CONFIG_SYS_CS4_MASK; 277 #endif 278 279 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \ 280 && defined(CONFIG_SYS_CS5_CTRL)) 281 gpio->par_cs |= GPIO_PAR_CS5; 282 fbcs->csar5 = CONFIG_SYS_CS5_BASE; 283 fbcs->cscr5 = CONFIG_SYS_CS5_CTRL; 284 fbcs->csmr5 = CONFIG_SYS_CS5_MASK; 285 #endif 286 287 #ifdef CONFIG_FSL_I2C 288 gpio->par_feci2c = GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA; 289 #endif 290 291 icache_enable(); 292 } 293 294 /* 295 * initialize higher level parts of CPU like timers 296 */ 297 int cpu_init_r(void) 298 { 299 return (0); 300 } 301 302 void uart_port_conf(int port) 303 { 304 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; 305 306 /* Setup Ports: */ 307 switch (port) { 308 case 0: 309 gpio->par_uart &= ~(GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0); 310 gpio->par_uart |= (GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0); 311 break; 312 case 1: 313 gpio->par_uart &= 314 ~(GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3)); 315 gpio->par_uart |= 316 (GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3)); 317 break; 318 case 2: 319 #ifdef CONFIG_SYS_UART2_ALT1_GPIO 320 gpio->par_timer &= 0x0F; 321 gpio->par_timer |= (GPIO_PAR_TIN3_URXD2 | GPIO_PAR_TIN2_UTXD2); 322 #elif defined(CONFIG_SYS_UART2_ALT2_GPIO) 323 gpio->par_feci2c &= 0xFF00; 324 gpio->par_feci2c |= (GPIO_PAR_FECI2C_SCL_UTXD2 | GPIO_PAR_FECI2C_SDA_URXD2); 325 #elif defined(CONFIG_SYS_UART2_ALT3_GPIO) 326 gpio->par_ssi &= 0xF0FF; 327 gpio->par_ssi |= (GPIO_PAR_SSI_RXD(2) | GPIO_PAR_SSI_TXD(2)); 328 #endif 329 break; 330 } 331 } 332 333 #if defined(CONFIG_CMD_NET) 334 int fecpin_setclear(struct eth_device *dev, int setclear) 335 { 336 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; 337 338 if (setclear) { 339 gpio->par_fec |= GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC; 340 gpio->par_feci2c |= 341 GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO; 342 } else { 343 gpio->par_fec &= ~(GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC); 344 gpio->par_feci2c &= 345 ~(GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO); 346 } 347 return 0; 348 } 349 #endif 350 #endif /* CONFIG_MCF532x */ 351