1a4145534SPeter Tyser /* 2a4145534SPeter Tyser * 3a4145534SPeter Tyser * (C) Copyright 2000-2003 4a4145534SPeter Tyser * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5a4145534SPeter Tyser * 6aa0d99fcSAlison Wang * (C) Copyright 2004-2008, 2012 Freescale Semiconductor, Inc. 7a4145534SPeter Tyser * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 8a4145534SPeter Tyser * 91a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 10a4145534SPeter Tyser */ 11a4145534SPeter Tyser 12a4145534SPeter Tyser #include <common.h> 13a4145534SPeter Tyser #include <watchdog.h> 14a4145534SPeter Tyser #include <asm/immap.h> 15aa0d99fcSAlison Wang #include <asm/io.h> 16a4145534SPeter Tyser 17a4145534SPeter Tyser #if defined(CONFIG_CMD_NET) 18a4145534SPeter Tyser #include <config.h> 19a4145534SPeter Tyser #include <net.h> 20a4145534SPeter Tyser #include <asm/fec.h> 21a4145534SPeter Tyser #endif 22a4145534SPeter Tyser 23a4145534SPeter Tyser #ifdef CONFIG_MCF5301x 24a4145534SPeter Tyser void cpu_init_f(void) 25a4145534SPeter Tyser { 26aa0d99fcSAlison Wang scm1_t *scm1 = (scm1_t *) MMAP_SCM1; 27aa0d99fcSAlison Wang gpio_t *gpio = (gpio_t *) MMAP_GPIO; 28aa0d99fcSAlison Wang fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; 29a4145534SPeter Tyser 30aa0d99fcSAlison Wang out_be32(&scm1->mpr, 0x77777777); 31aa0d99fcSAlison Wang out_be32(&scm1->pacra, 0); 32aa0d99fcSAlison Wang out_be32(&scm1->pacrb, 0); 33aa0d99fcSAlison Wang out_be32(&scm1->pacrc, 0); 34aa0d99fcSAlison Wang out_be32(&scm1->pacrd, 0); 35aa0d99fcSAlison Wang out_be32(&scm1->pacre, 0); 36aa0d99fcSAlison Wang out_be32(&scm1->pacrf, 0); 37aa0d99fcSAlison Wang out_be32(&scm1->pacrg, 0); 38a4145534SPeter Tyser 39a4145534SPeter Tyser #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ 40a4145534SPeter Tyser && defined(CONFIG_SYS_CS0_CTRL)) 41aa0d99fcSAlison Wang setbits_8(&gpio->par_cs, GPIO_PAR_CS0_CS0); 42aa0d99fcSAlison Wang out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); 43aa0d99fcSAlison Wang out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); 44aa0d99fcSAlison Wang out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); 45a4145534SPeter Tyser #endif 46a4145534SPeter Tyser 47a4145534SPeter Tyser #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ 48a4145534SPeter Tyser && defined(CONFIG_SYS_CS1_CTRL)) 49aa0d99fcSAlison Wang setbits_8(&gpio->par_cs, GPIO_PAR_CS1_CS1); 50aa0d99fcSAlison Wang out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); 51aa0d99fcSAlison Wang out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); 52aa0d99fcSAlison Wang out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); 53a4145534SPeter Tyser #endif 54a4145534SPeter Tyser 55a4145534SPeter Tyser #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ 56a4145534SPeter Tyser && defined(CONFIG_SYS_CS2_CTRL)) 57aa0d99fcSAlison Wang out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); 58aa0d99fcSAlison Wang out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); 59aa0d99fcSAlison Wang out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); 60a4145534SPeter Tyser #endif 61a4145534SPeter Tyser 62a4145534SPeter Tyser #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ 63a4145534SPeter Tyser && defined(CONFIG_SYS_CS3_CTRL)) 64aa0d99fcSAlison Wang out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); 65aa0d99fcSAlison Wang out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); 66aa0d99fcSAlison Wang out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); 67a4145534SPeter Tyser #endif 68a4145534SPeter Tyser 69a4145534SPeter Tyser #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ 70a4145534SPeter Tyser && defined(CONFIG_SYS_CS4_CTRL)) 71aa0d99fcSAlison Wang setbits_8(&gpio->par_cs, GPIO_PAR_CS4); 72aa0d99fcSAlison Wang out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE); 73aa0d99fcSAlison Wang out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL); 74aa0d99fcSAlison Wang out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK); 75a4145534SPeter Tyser #endif 76a4145534SPeter Tyser 77a4145534SPeter Tyser #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \ 78a4145534SPeter Tyser && defined(CONFIG_SYS_CS5_CTRL)) 79aa0d99fcSAlison Wang setbits_8(&gpio->par_cs, GPIO_PAR_CS5); 80aa0d99fcSAlison Wang out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE); 81aa0d99fcSAlison Wang out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL); 82aa0d99fcSAlison Wang out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK); 83a4145534SPeter Tyser #endif 84a4145534SPeter Tyser 8500f792e0SHeiko Schocher #ifdef CONFIG_SYS_I2C_FSL 86aa0d99fcSAlison Wang out_8(&gpio->par_feci2c, 87aa0d99fcSAlison Wang GPIO_PAR_FECI2C_SDA_SDA | GPIO_PAR_FECI2C_SCL_SCL); 88a4145534SPeter Tyser #endif 89a4145534SPeter Tyser 90a4145534SPeter Tyser icache_enable(); 91a4145534SPeter Tyser } 92a4145534SPeter Tyser 93a4145534SPeter Tyser /* initialize higher level parts of CPU like timers */ 94a4145534SPeter Tyser int cpu_init_r(void) 95a4145534SPeter Tyser { 96a4145534SPeter Tyser #ifdef CONFIG_MCFFEC 97aa0d99fcSAlison Wang ccm_t *ccm = (ccm_t *) MMAP_CCM; 98a4145534SPeter Tyser #endif 99a4145534SPeter Tyser #ifdef CONFIG_MCFRTC 100aa0d99fcSAlison Wang rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE); 101aa0d99fcSAlison Wang rtcex_t *rtcex = (rtcex_t *) &rtc->extended; 102a4145534SPeter Tyser 103aa0d99fcSAlison Wang out_be32(&rtcex->gocu, CONFIG_SYS_RTC_CNT); 104aa0d99fcSAlison Wang out_be32(&rtcex->gocl, CONFIG_SYS_RTC_SETUP); 105a4145534SPeter Tyser 106a4145534SPeter Tyser #endif 107a4145534SPeter Tyser #ifdef CONFIG_MCFFEC 108a4145534SPeter Tyser if (CONFIG_SYS_FEC0_MIIBASE != CONFIG_SYS_FEC1_MIIBASE) 109aa0d99fcSAlison Wang setbits_be16(&ccm->misccr, CCM_MISCCR_FECM); 110a4145534SPeter Tyser else 111aa0d99fcSAlison Wang clrbits_be16(&ccm->misccr, CCM_MISCCR_FECM); 112a4145534SPeter Tyser #endif 113a4145534SPeter Tyser 114a4145534SPeter Tyser return (0); 115a4145534SPeter Tyser } 116a4145534SPeter Tyser 117a4145534SPeter Tyser void uart_port_conf(int port) 118a4145534SPeter Tyser { 119aa0d99fcSAlison Wang gpio_t *gpio = (gpio_t *) MMAP_GPIO; 120a4145534SPeter Tyser 121a4145534SPeter Tyser /* Setup Ports: */ 122a4145534SPeter Tyser switch (port) { 123a4145534SPeter Tyser case 0: 124aa0d99fcSAlison Wang clrbits_8(&gpio->par_uart, 125aa0d99fcSAlison Wang GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD); 126aa0d99fcSAlison Wang setbits_8(&gpio->par_uart, 127aa0d99fcSAlison Wang GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD); 128a4145534SPeter Tyser break; 129a4145534SPeter Tyser case 1: 130a4145534SPeter Tyser #ifdef CONFIG_SYS_UART1_ALT1_GPIO 131aa0d99fcSAlison Wang clrbits_8(&gpio->par_simp1h, 132aa0d99fcSAlison Wang GPIO_PAR_SIMP1H_DATA1_UNMASK | 133a4145534SPeter Tyser GPIO_PAR_SIMP1H_VEN1_UNMASK); 134aa0d99fcSAlison Wang setbits_8(&gpio->par_simp1h, 135aa0d99fcSAlison Wang GPIO_PAR_SIMP1H_DATA1_U1TXD | 136aa0d99fcSAlison Wang GPIO_PAR_SIMP1H_VEN1_U1RXD); 137a4145534SPeter Tyser #elif defined(CONFIG_SYS_UART1_ALT2_GPIO) 138aa0d99fcSAlison Wang clrbits_8(&gpio->par_ssih, 139aa0d99fcSAlison Wang GPIO_PAR_SSIH_RXD_UNMASK | 140aa0d99fcSAlison Wang GPIO_PAR_SSIH_TXD_UNMASK); 141aa0d99fcSAlison Wang setbits_8(&gpio->par_ssih, 142aa0d99fcSAlison Wang GPIO_PAR_SSIH_RXD_U1RXD | 143aa0d99fcSAlison Wang GPIO_PAR_SSIH_TXD_U1TXD); 144a4145534SPeter Tyser #endif 145a4145534SPeter Tyser break; 146a4145534SPeter Tyser case 2: 147a4145534SPeter Tyser #ifdef CONFIG_SYS_UART2_PRI_GPIO 148aa0d99fcSAlison Wang setbits_8(&gpio->par_uart, 149aa0d99fcSAlison Wang GPIO_PAR_UART_U2TXD | 150aa0d99fcSAlison Wang GPIO_PAR_UART_U2RXD); 151a4145534SPeter Tyser #elif defined(CONFIG_SYS_UART2_ALT1_GPIO) 152aa0d99fcSAlison Wang clrbits_8(&gpio->par_dspih, 153aa0d99fcSAlison Wang GPIO_PAR_DSPIH_SIN_UNMASK | 154aa0d99fcSAlison Wang GPIO_PAR_DSPIH_SOUT_UNMASK); 155aa0d99fcSAlison Wang setbits_8(&gpio->par_dspih, 156aa0d99fcSAlison Wang GPIO_PAR_DSPIH_SIN_U2RXD | 157aa0d99fcSAlison Wang GPIO_PAR_DSPIH_SOUT_U2TXD); 158a4145534SPeter Tyser #elif defined(CONFIG_SYS_UART2_ALT2_GPIO) 159aa0d99fcSAlison Wang clrbits_8(&gpio->par_feci2c, 160aa0d99fcSAlison Wang GPIO_PAR_FECI2C_SDA_UNMASK | 161aa0d99fcSAlison Wang GPIO_PAR_FECI2C_SCL_UNMASK); 162aa0d99fcSAlison Wang setbits_8(&gpio->par_feci2c, 163aa0d99fcSAlison Wang GPIO_PAR_FECI2C_SDA_U2TXD | 164aa0d99fcSAlison Wang GPIO_PAR_FECI2C_SCL_U2RXD); 165a4145534SPeter Tyser #endif 166a4145534SPeter Tyser break; 167a4145534SPeter Tyser } 168a4145534SPeter Tyser } 169a4145534SPeter Tyser 170a4145534SPeter Tyser #if defined(CONFIG_CMD_NET) 171a4145534SPeter Tyser int fecpin_setclear(struct eth_device *dev, int setclear) 172a4145534SPeter Tyser { 173aa0d99fcSAlison Wang gpio_t *gpio = (gpio_t *) MMAP_GPIO; 174a4145534SPeter Tyser struct fec_info_s *info = (struct fec_info_s *)dev->priv; 175a4145534SPeter Tyser 176a4145534SPeter Tyser if (setclear) { 177a4145534SPeter Tyser if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { 178aa0d99fcSAlison Wang setbits_8(&gpio->par_fec, 179aa0d99fcSAlison Wang GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC); 180aa0d99fcSAlison Wang setbits_8(&gpio->par_feci2c, 181aa0d99fcSAlison Wang GPIO_PAR_FECI2C_MDC0 | GPIO_PAR_FECI2C_MDIO0); 182a4145534SPeter Tyser } else { 183aa0d99fcSAlison Wang setbits_8(&gpio->par_fec, 184aa0d99fcSAlison Wang GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC); 185aa0d99fcSAlison Wang setbits_8(&gpio->par_feci2c, 186aa0d99fcSAlison Wang GPIO_PAR_FECI2C_MDC1 | GPIO_PAR_FECI2C_MDIO1); 187a4145534SPeter Tyser } 188a4145534SPeter Tyser } else { 189a4145534SPeter Tyser if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { 190aa0d99fcSAlison Wang clrbits_8(&gpio->par_fec, 191aa0d99fcSAlison Wang GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC); 192aa0d99fcSAlison Wang clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII0_UNMASK); 193a4145534SPeter Tyser } else { 194aa0d99fcSAlison Wang clrbits_8(&gpio->par_fec, 195aa0d99fcSAlison Wang GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC); 196aa0d99fcSAlison Wang clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII1_UNMASK); 197a4145534SPeter Tyser } 198a4145534SPeter Tyser } 199a4145534SPeter Tyser return 0; 200a4145534SPeter Tyser } 201a4145534SPeter Tyser #endif /* CONFIG_CMD_NET */ 202a4145534SPeter Tyser #endif /* CONFIG_MCF5301x */ 203a4145534SPeter Tyser 204a4145534SPeter Tyser #ifdef CONFIG_MCF532x 205a4145534SPeter Tyser void cpu_init_f(void) 206a4145534SPeter Tyser { 207aa0d99fcSAlison Wang scm1_t *scm1 = (scm1_t *) MMAP_SCM1; 208aa0d99fcSAlison Wang scm2_t *scm2 = (scm2_t *) MMAP_SCM2; 209aa0d99fcSAlison Wang gpio_t *gpio = (gpio_t *) MMAP_GPIO; 210aa0d99fcSAlison Wang fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; 211*ddc94378SSimon Glass #ifndef CONFIG_WATCHDOG 212aa0d99fcSAlison Wang wdog_t *wdog = (wdog_t *) MMAP_WDOG; 213a4145534SPeter Tyser 214a4145534SPeter Tyser /* watchdog is enabled by default - disable the watchdog */ 215aa0d99fcSAlison Wang out_be16(&wdog->cr, 0); 216a4145534SPeter Tyser #endif 217a4145534SPeter Tyser 218aa0d99fcSAlison Wang out_be32(&scm1->mpr0, 0x77777777); 219aa0d99fcSAlison Wang out_be32(&scm2->pacra, 0); 220aa0d99fcSAlison Wang out_be32(&scm2->pacrb, 0); 221aa0d99fcSAlison Wang out_be32(&scm2->pacrc, 0); 222aa0d99fcSAlison Wang out_be32(&scm2->pacrd, 0); 223aa0d99fcSAlison Wang out_be32(&scm2->pacre, 0); 224aa0d99fcSAlison Wang out_be32(&scm2->pacrf, 0); 225aa0d99fcSAlison Wang out_be32(&scm2->pacrg, 0); 226aa0d99fcSAlison Wang out_be32(&scm1->pacrh, 0); 227a4145534SPeter Tyser 228a4145534SPeter Tyser /* Port configuration */ 229aa0d99fcSAlison Wang out_8(&gpio->par_cs, 0); 230a4145534SPeter Tyser 231a4145534SPeter Tyser #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ 232a4145534SPeter Tyser && defined(CONFIG_SYS_CS0_CTRL)) 233aa0d99fcSAlison Wang out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); 234aa0d99fcSAlison Wang out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); 235aa0d99fcSAlison Wang out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); 236a4145534SPeter Tyser #endif 237a4145534SPeter Tyser 238a4145534SPeter Tyser #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ 239a4145534SPeter Tyser && defined(CONFIG_SYS_CS1_CTRL)) 240a4145534SPeter Tyser /* Latch chipselect */ 241aa0d99fcSAlison Wang setbits_8(&gpio->par_cs, GPIO_PAR_CS1); 242aa0d99fcSAlison Wang out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); 243aa0d99fcSAlison Wang out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); 244aa0d99fcSAlison Wang out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); 245a4145534SPeter Tyser #endif 246a4145534SPeter Tyser 247a4145534SPeter Tyser #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ 248a4145534SPeter Tyser && defined(CONFIG_SYS_CS2_CTRL)) 249aa0d99fcSAlison Wang setbits_8(&gpio->par_cs, GPIO_PAR_CS2); 250aa0d99fcSAlison Wang out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); 251aa0d99fcSAlison Wang out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); 252aa0d99fcSAlison Wang out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); 253a4145534SPeter Tyser #endif 254a4145534SPeter Tyser 255a4145534SPeter Tyser #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ 256a4145534SPeter Tyser && defined(CONFIG_SYS_CS3_CTRL)) 257aa0d99fcSAlison Wang setbits_8(&gpio->par_cs, GPIO_PAR_CS3); 258aa0d99fcSAlison Wang out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); 259aa0d99fcSAlison Wang out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); 260aa0d99fcSAlison Wang out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); 261a4145534SPeter Tyser #endif 262a4145534SPeter Tyser 263a4145534SPeter Tyser #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ 264a4145534SPeter Tyser && defined(CONFIG_SYS_CS4_CTRL)) 265aa0d99fcSAlison Wang setbits_8(&gpio->par_cs, GPIO_PAR_CS4); 266aa0d99fcSAlison Wang out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE); 267aa0d99fcSAlison Wang out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL); 268aa0d99fcSAlison Wang out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK); 269a4145534SPeter Tyser #endif 270a4145534SPeter Tyser 271a4145534SPeter Tyser #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \ 272a4145534SPeter Tyser && defined(CONFIG_SYS_CS5_CTRL)) 273aa0d99fcSAlison Wang setbits_8(&gpio->par_cs, GPIO_PAR_CS5); 274aa0d99fcSAlison Wang out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE); 275aa0d99fcSAlison Wang out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL); 276aa0d99fcSAlison Wang out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK); 277a4145534SPeter Tyser #endif 278a4145534SPeter Tyser 27900f792e0SHeiko Schocher #ifdef CONFIG_SYS_I2C_FSL 280aa0d99fcSAlison Wang out_8(&gpio->par_feci2c, 281aa0d99fcSAlison Wang GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA); 282a4145534SPeter Tyser #endif 283a4145534SPeter Tyser 284a4145534SPeter Tyser icache_enable(); 285a4145534SPeter Tyser } 286a4145534SPeter Tyser 287a4145534SPeter Tyser /* 288a4145534SPeter Tyser * initialize higher level parts of CPU like timers 289a4145534SPeter Tyser */ 290a4145534SPeter Tyser int cpu_init_r(void) 291a4145534SPeter Tyser { 292a4145534SPeter Tyser return (0); 293a4145534SPeter Tyser } 294a4145534SPeter Tyser 295a4145534SPeter Tyser void uart_port_conf(int port) 296a4145534SPeter Tyser { 297aa0d99fcSAlison Wang gpio_t *gpio = (gpio_t *) MMAP_GPIO; 298a4145534SPeter Tyser 299a4145534SPeter Tyser /* Setup Ports: */ 300a4145534SPeter Tyser switch (port) { 301a4145534SPeter Tyser case 0: 302aa0d99fcSAlison Wang clrbits_be16(&gpio->par_uart, 303aa0d99fcSAlison Wang GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0); 304aa0d99fcSAlison Wang setbits_be16(&gpio->par_uart, 305aa0d99fcSAlison Wang GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0); 306a4145534SPeter Tyser break; 307a4145534SPeter Tyser case 1: 308aa0d99fcSAlison Wang clrbits_be16(&gpio->par_uart, 309aa0d99fcSAlison Wang GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3)); 310aa0d99fcSAlison Wang setbits_be16(&gpio->par_uart, 311aa0d99fcSAlison Wang GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3)); 312a4145534SPeter Tyser break; 313a4145534SPeter Tyser case 2: 314a4145534SPeter Tyser #ifdef CONFIG_SYS_UART2_ALT1_GPIO 315aa0d99fcSAlison Wang clrbits_8(&gpio->par_timer, 0xf0); 316aa0d99fcSAlison Wang setbits_8(&gpio->par_timer, 317aa0d99fcSAlison Wang GPIO_PAR_TIN3_URXD2 | GPIO_PAR_TIN2_UTXD2); 318a4145534SPeter Tyser #elif defined(CONFIG_SYS_UART2_ALT2_GPIO) 319aa0d99fcSAlison Wang clrbits_8(&gpio->par_feci2c, 0x00ff); 320aa0d99fcSAlison Wang setbits_8(&gpio->par_feci2c, 321aa0d99fcSAlison Wang GPIO_PAR_FECI2C_SCL_UTXD2 | GPIO_PAR_FECI2C_SDA_URXD2); 322a4145534SPeter Tyser #elif defined(CONFIG_SYS_UART2_ALT3_GPIO) 323aa0d99fcSAlison Wang clrbits_be16(&gpio->par_ssi, 0x0f00); 324aa0d99fcSAlison Wang setbits_be16(&gpio->par_ssi, 325aa0d99fcSAlison Wang GPIO_PAR_SSI_RXD(2) | GPIO_PAR_SSI_TXD(2)); 326a4145534SPeter Tyser #endif 327a4145534SPeter Tyser break; 328a4145534SPeter Tyser } 329a4145534SPeter Tyser } 330a4145534SPeter Tyser 331a4145534SPeter Tyser #if defined(CONFIG_CMD_NET) 332a4145534SPeter Tyser int fecpin_setclear(struct eth_device *dev, int setclear) 333a4145534SPeter Tyser { 334aa0d99fcSAlison Wang gpio_t *gpio = (gpio_t *) MMAP_GPIO; 335a4145534SPeter Tyser 336a4145534SPeter Tyser if (setclear) { 337aa0d99fcSAlison Wang setbits_8(&gpio->par_fec, 338aa0d99fcSAlison Wang GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC); 339aa0d99fcSAlison Wang setbits_8(&gpio->par_feci2c, 340aa0d99fcSAlison Wang GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO); 341a4145534SPeter Tyser } else { 342aa0d99fcSAlison Wang clrbits_8(&gpio->par_fec, 343aa0d99fcSAlison Wang GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC); 344aa0d99fcSAlison Wang clrbits_8(&gpio->par_feci2c, 345aa0d99fcSAlison Wang GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO); 346a4145534SPeter Tyser } 347a4145534SPeter Tyser return 0; 348a4145534SPeter Tyser } 349a4145534SPeter Tyser #endif 350a4145534SPeter Tyser #endif /* CONFIG_MCF532x */ 351