1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 2a4145534SPeter Tyser /* 3a4145534SPeter Tyser * 4a4145534SPeter Tyser * (C) Copyright 2000-2003 5a4145534SPeter Tyser * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6a4145534SPeter Tyser * 7aa0d99fcSAlison Wang * (C) Copyright 2004-2008, 2012 Freescale Semiconductor, Inc. 8a4145534SPeter Tyser * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 9a4145534SPeter Tyser */ 10a4145534SPeter Tyser 11a4145534SPeter Tyser #include <common.h> 12a4145534SPeter Tyser #include <watchdog.h> 13a4145534SPeter Tyser #include <asm/immap.h> 14aa0d99fcSAlison Wang #include <asm/io.h> 15a4145534SPeter Tyser 16a4145534SPeter Tyser #if defined(CONFIG_CMD_NET) 17a4145534SPeter Tyser #include <config.h> 18a4145534SPeter Tyser #include <net.h> 19a4145534SPeter Tyser #include <asm/fec.h> 20a4145534SPeter Tyser #endif 21a4145534SPeter Tyser 22a4145534SPeter Tyser #ifdef CONFIG_MCF5301x 23a4145534SPeter Tyser void cpu_init_f(void) 24a4145534SPeter Tyser { 25aa0d99fcSAlison Wang scm1_t *scm1 = (scm1_t *) MMAP_SCM1; 26aa0d99fcSAlison Wang gpio_t *gpio = (gpio_t *) MMAP_GPIO; 27aa0d99fcSAlison Wang fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; 28a4145534SPeter Tyser 29aa0d99fcSAlison Wang out_be32(&scm1->mpr, 0x77777777); 30aa0d99fcSAlison Wang out_be32(&scm1->pacra, 0); 31aa0d99fcSAlison Wang out_be32(&scm1->pacrb, 0); 32aa0d99fcSAlison Wang out_be32(&scm1->pacrc, 0); 33aa0d99fcSAlison Wang out_be32(&scm1->pacrd, 0); 34aa0d99fcSAlison Wang out_be32(&scm1->pacre, 0); 35aa0d99fcSAlison Wang out_be32(&scm1->pacrf, 0); 36aa0d99fcSAlison Wang out_be32(&scm1->pacrg, 0); 37a4145534SPeter Tyser 38a4145534SPeter Tyser #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ 39a4145534SPeter Tyser && defined(CONFIG_SYS_CS0_CTRL)) 40aa0d99fcSAlison Wang setbits_8(&gpio->par_cs, GPIO_PAR_CS0_CS0); 41aa0d99fcSAlison Wang out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); 42aa0d99fcSAlison Wang out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); 43aa0d99fcSAlison Wang out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); 44a4145534SPeter Tyser #endif 45a4145534SPeter Tyser 46a4145534SPeter Tyser #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ 47a4145534SPeter Tyser && defined(CONFIG_SYS_CS1_CTRL)) 48aa0d99fcSAlison Wang setbits_8(&gpio->par_cs, GPIO_PAR_CS1_CS1); 49aa0d99fcSAlison Wang out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); 50aa0d99fcSAlison Wang out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); 51aa0d99fcSAlison Wang out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); 52a4145534SPeter Tyser #endif 53a4145534SPeter Tyser 54a4145534SPeter Tyser #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ 55a4145534SPeter Tyser && defined(CONFIG_SYS_CS2_CTRL)) 56aa0d99fcSAlison Wang out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); 57aa0d99fcSAlison Wang out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); 58aa0d99fcSAlison Wang out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); 59a4145534SPeter Tyser #endif 60a4145534SPeter Tyser 61a4145534SPeter Tyser #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ 62a4145534SPeter Tyser && defined(CONFIG_SYS_CS3_CTRL)) 63aa0d99fcSAlison Wang out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); 64aa0d99fcSAlison Wang out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); 65aa0d99fcSAlison Wang out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); 66a4145534SPeter Tyser #endif 67a4145534SPeter Tyser 68a4145534SPeter Tyser #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ 69a4145534SPeter Tyser && defined(CONFIG_SYS_CS4_CTRL)) 70aa0d99fcSAlison Wang setbits_8(&gpio->par_cs, GPIO_PAR_CS4); 71aa0d99fcSAlison Wang out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE); 72aa0d99fcSAlison Wang out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL); 73aa0d99fcSAlison Wang out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK); 74a4145534SPeter Tyser #endif 75a4145534SPeter Tyser 76a4145534SPeter Tyser #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \ 77a4145534SPeter Tyser && defined(CONFIG_SYS_CS5_CTRL)) 78aa0d99fcSAlison Wang setbits_8(&gpio->par_cs, GPIO_PAR_CS5); 79aa0d99fcSAlison Wang out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE); 80aa0d99fcSAlison Wang out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL); 81aa0d99fcSAlison Wang out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK); 82a4145534SPeter Tyser #endif 83a4145534SPeter Tyser 8400f792e0SHeiko Schocher #ifdef CONFIG_SYS_I2C_FSL 85aa0d99fcSAlison Wang out_8(&gpio->par_feci2c, 86aa0d99fcSAlison Wang GPIO_PAR_FECI2C_SDA_SDA | GPIO_PAR_FECI2C_SCL_SCL); 87a4145534SPeter Tyser #endif 88a4145534SPeter Tyser 89a4145534SPeter Tyser icache_enable(); 90a4145534SPeter Tyser } 91a4145534SPeter Tyser 92a4145534SPeter Tyser /* initialize higher level parts of CPU like timers */ 93a4145534SPeter Tyser int cpu_init_r(void) 94a4145534SPeter Tyser { 95a4145534SPeter Tyser #ifdef CONFIG_MCFFEC 96aa0d99fcSAlison Wang ccm_t *ccm = (ccm_t *) MMAP_CCM; 97a4145534SPeter Tyser #endif 98a4145534SPeter Tyser #ifdef CONFIG_MCFRTC 99aa0d99fcSAlison Wang rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE); 100aa0d99fcSAlison Wang rtcex_t *rtcex = (rtcex_t *) &rtc->extended; 101a4145534SPeter Tyser 102aa0d99fcSAlison Wang out_be32(&rtcex->gocu, CONFIG_SYS_RTC_CNT); 103aa0d99fcSAlison Wang out_be32(&rtcex->gocl, CONFIG_SYS_RTC_SETUP); 104a4145534SPeter Tyser 105a4145534SPeter Tyser #endif 106a4145534SPeter Tyser #ifdef CONFIG_MCFFEC 107a4145534SPeter Tyser if (CONFIG_SYS_FEC0_MIIBASE != CONFIG_SYS_FEC1_MIIBASE) 108aa0d99fcSAlison Wang setbits_be16(&ccm->misccr, CCM_MISCCR_FECM); 109a4145534SPeter Tyser else 110aa0d99fcSAlison Wang clrbits_be16(&ccm->misccr, CCM_MISCCR_FECM); 111a4145534SPeter Tyser #endif 112a4145534SPeter Tyser 113a4145534SPeter Tyser return (0); 114a4145534SPeter Tyser } 115a4145534SPeter Tyser 116a4145534SPeter Tyser void uart_port_conf(int port) 117a4145534SPeter Tyser { 118aa0d99fcSAlison Wang gpio_t *gpio = (gpio_t *) MMAP_GPIO; 119a4145534SPeter Tyser 120a4145534SPeter Tyser /* Setup Ports: */ 121a4145534SPeter Tyser switch (port) { 122a4145534SPeter Tyser case 0: 123aa0d99fcSAlison Wang clrbits_8(&gpio->par_uart, 124aa0d99fcSAlison Wang GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD); 125aa0d99fcSAlison Wang setbits_8(&gpio->par_uart, 126aa0d99fcSAlison Wang GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD); 127a4145534SPeter Tyser break; 128a4145534SPeter Tyser case 1: 129a4145534SPeter Tyser #ifdef CONFIG_SYS_UART1_ALT1_GPIO 130aa0d99fcSAlison Wang clrbits_8(&gpio->par_simp1h, 131aa0d99fcSAlison Wang GPIO_PAR_SIMP1H_DATA1_UNMASK | 132a4145534SPeter Tyser GPIO_PAR_SIMP1H_VEN1_UNMASK); 133aa0d99fcSAlison Wang setbits_8(&gpio->par_simp1h, 134aa0d99fcSAlison Wang GPIO_PAR_SIMP1H_DATA1_U1TXD | 135aa0d99fcSAlison Wang GPIO_PAR_SIMP1H_VEN1_U1RXD); 136a4145534SPeter Tyser #elif defined(CONFIG_SYS_UART1_ALT2_GPIO) 137aa0d99fcSAlison Wang clrbits_8(&gpio->par_ssih, 138aa0d99fcSAlison Wang GPIO_PAR_SSIH_RXD_UNMASK | 139aa0d99fcSAlison Wang GPIO_PAR_SSIH_TXD_UNMASK); 140aa0d99fcSAlison Wang setbits_8(&gpio->par_ssih, 141aa0d99fcSAlison Wang GPIO_PAR_SSIH_RXD_U1RXD | 142aa0d99fcSAlison Wang GPIO_PAR_SSIH_TXD_U1TXD); 143a4145534SPeter Tyser #endif 144a4145534SPeter Tyser break; 145a4145534SPeter Tyser case 2: 146a4145534SPeter Tyser #ifdef CONFIG_SYS_UART2_PRI_GPIO 147aa0d99fcSAlison Wang setbits_8(&gpio->par_uart, 148aa0d99fcSAlison Wang GPIO_PAR_UART_U2TXD | 149aa0d99fcSAlison Wang GPIO_PAR_UART_U2RXD); 150a4145534SPeter Tyser #elif defined(CONFIG_SYS_UART2_ALT1_GPIO) 151aa0d99fcSAlison Wang clrbits_8(&gpio->par_dspih, 152aa0d99fcSAlison Wang GPIO_PAR_DSPIH_SIN_UNMASK | 153aa0d99fcSAlison Wang GPIO_PAR_DSPIH_SOUT_UNMASK); 154aa0d99fcSAlison Wang setbits_8(&gpio->par_dspih, 155aa0d99fcSAlison Wang GPIO_PAR_DSPIH_SIN_U2RXD | 156aa0d99fcSAlison Wang GPIO_PAR_DSPIH_SOUT_U2TXD); 157a4145534SPeter Tyser #elif defined(CONFIG_SYS_UART2_ALT2_GPIO) 158aa0d99fcSAlison Wang clrbits_8(&gpio->par_feci2c, 159aa0d99fcSAlison Wang GPIO_PAR_FECI2C_SDA_UNMASK | 160aa0d99fcSAlison Wang GPIO_PAR_FECI2C_SCL_UNMASK); 161aa0d99fcSAlison Wang setbits_8(&gpio->par_feci2c, 162aa0d99fcSAlison Wang GPIO_PAR_FECI2C_SDA_U2TXD | 163aa0d99fcSAlison Wang GPIO_PAR_FECI2C_SCL_U2RXD); 164a4145534SPeter Tyser #endif 165a4145534SPeter Tyser break; 166a4145534SPeter Tyser } 167a4145534SPeter Tyser } 168a4145534SPeter Tyser 169a4145534SPeter Tyser #if defined(CONFIG_CMD_NET) 170a4145534SPeter Tyser int fecpin_setclear(struct eth_device *dev, int setclear) 171a4145534SPeter Tyser { 172aa0d99fcSAlison Wang gpio_t *gpio = (gpio_t *) MMAP_GPIO; 173a4145534SPeter Tyser struct fec_info_s *info = (struct fec_info_s *)dev->priv; 174a4145534SPeter Tyser 175a4145534SPeter Tyser if (setclear) { 176a4145534SPeter Tyser if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { 177aa0d99fcSAlison Wang setbits_8(&gpio->par_fec, 178aa0d99fcSAlison Wang GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC); 179aa0d99fcSAlison Wang setbits_8(&gpio->par_feci2c, 180aa0d99fcSAlison Wang GPIO_PAR_FECI2C_MDC0 | GPIO_PAR_FECI2C_MDIO0); 181a4145534SPeter Tyser } else { 182aa0d99fcSAlison Wang setbits_8(&gpio->par_fec, 183aa0d99fcSAlison Wang GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC); 184aa0d99fcSAlison Wang setbits_8(&gpio->par_feci2c, 185aa0d99fcSAlison Wang GPIO_PAR_FECI2C_MDC1 | GPIO_PAR_FECI2C_MDIO1); 186a4145534SPeter Tyser } 187a4145534SPeter Tyser } else { 188a4145534SPeter Tyser if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { 189aa0d99fcSAlison Wang clrbits_8(&gpio->par_fec, 190aa0d99fcSAlison Wang GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC); 191aa0d99fcSAlison Wang clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII0_UNMASK); 192a4145534SPeter Tyser } else { 193aa0d99fcSAlison Wang clrbits_8(&gpio->par_fec, 194aa0d99fcSAlison Wang GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC); 195aa0d99fcSAlison Wang clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII1_UNMASK); 196a4145534SPeter Tyser } 197a4145534SPeter Tyser } 198a4145534SPeter Tyser return 0; 199a4145534SPeter Tyser } 200a4145534SPeter Tyser #endif /* CONFIG_CMD_NET */ 201a4145534SPeter Tyser #endif /* CONFIG_MCF5301x */ 202a4145534SPeter Tyser 203a4145534SPeter Tyser #ifdef CONFIG_MCF532x 204a4145534SPeter Tyser void cpu_init_f(void) 205a4145534SPeter Tyser { 206aa0d99fcSAlison Wang scm1_t *scm1 = (scm1_t *) MMAP_SCM1; 207aa0d99fcSAlison Wang scm2_t *scm2 = (scm2_t *) MMAP_SCM2; 208aa0d99fcSAlison Wang gpio_t *gpio = (gpio_t *) MMAP_GPIO; 209aa0d99fcSAlison Wang fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; 210ddc94378SSimon Glass #ifndef CONFIG_WATCHDOG 211aa0d99fcSAlison Wang wdog_t *wdog = (wdog_t *) MMAP_WDOG; 212a4145534SPeter Tyser 213a4145534SPeter Tyser /* watchdog is enabled by default - disable the watchdog */ 214aa0d99fcSAlison Wang out_be16(&wdog->cr, 0); 215a4145534SPeter Tyser #endif 216a4145534SPeter Tyser 217aa0d99fcSAlison Wang out_be32(&scm1->mpr0, 0x77777777); 218aa0d99fcSAlison Wang out_be32(&scm2->pacra, 0); 219aa0d99fcSAlison Wang out_be32(&scm2->pacrb, 0); 220aa0d99fcSAlison Wang out_be32(&scm2->pacrc, 0); 221aa0d99fcSAlison Wang out_be32(&scm2->pacrd, 0); 222aa0d99fcSAlison Wang out_be32(&scm2->pacre, 0); 223aa0d99fcSAlison Wang out_be32(&scm2->pacrf, 0); 224aa0d99fcSAlison Wang out_be32(&scm2->pacrg, 0); 225aa0d99fcSAlison Wang out_be32(&scm1->pacrh, 0); 226a4145534SPeter Tyser 227a4145534SPeter Tyser /* Port configuration */ 228aa0d99fcSAlison Wang out_8(&gpio->par_cs, 0); 229a4145534SPeter Tyser 230a4145534SPeter Tyser #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ 231a4145534SPeter Tyser && defined(CONFIG_SYS_CS0_CTRL)) 232aa0d99fcSAlison Wang out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); 233aa0d99fcSAlison Wang out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); 234aa0d99fcSAlison Wang out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); 235a4145534SPeter Tyser #endif 236a4145534SPeter Tyser 237a4145534SPeter Tyser #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ 238a4145534SPeter Tyser && defined(CONFIG_SYS_CS1_CTRL)) 239a4145534SPeter Tyser /* Latch chipselect */ 240aa0d99fcSAlison Wang setbits_8(&gpio->par_cs, GPIO_PAR_CS1); 241aa0d99fcSAlison Wang out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); 242aa0d99fcSAlison Wang out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); 243aa0d99fcSAlison Wang out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); 244a4145534SPeter Tyser #endif 245a4145534SPeter Tyser 246a4145534SPeter Tyser #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ 247a4145534SPeter Tyser && defined(CONFIG_SYS_CS2_CTRL)) 248aa0d99fcSAlison Wang setbits_8(&gpio->par_cs, GPIO_PAR_CS2); 249aa0d99fcSAlison Wang out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); 250aa0d99fcSAlison Wang out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); 251aa0d99fcSAlison Wang out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); 252a4145534SPeter Tyser #endif 253a4145534SPeter Tyser 254a4145534SPeter Tyser #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ 255a4145534SPeter Tyser && defined(CONFIG_SYS_CS3_CTRL)) 256aa0d99fcSAlison Wang setbits_8(&gpio->par_cs, GPIO_PAR_CS3); 257aa0d99fcSAlison Wang out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); 258aa0d99fcSAlison Wang out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); 259aa0d99fcSAlison Wang out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); 260a4145534SPeter Tyser #endif 261a4145534SPeter Tyser 262a4145534SPeter Tyser #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ 263a4145534SPeter Tyser && defined(CONFIG_SYS_CS4_CTRL)) 264aa0d99fcSAlison Wang setbits_8(&gpio->par_cs, GPIO_PAR_CS4); 265aa0d99fcSAlison Wang out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE); 266aa0d99fcSAlison Wang out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL); 267aa0d99fcSAlison Wang out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK); 268a4145534SPeter Tyser #endif 269a4145534SPeter Tyser 270a4145534SPeter Tyser #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \ 271a4145534SPeter Tyser && defined(CONFIG_SYS_CS5_CTRL)) 272aa0d99fcSAlison Wang setbits_8(&gpio->par_cs, GPIO_PAR_CS5); 273aa0d99fcSAlison Wang out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE); 274aa0d99fcSAlison Wang out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL); 275aa0d99fcSAlison Wang out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK); 276a4145534SPeter Tyser #endif 277a4145534SPeter Tyser 27800f792e0SHeiko Schocher #ifdef CONFIG_SYS_I2C_FSL 279aa0d99fcSAlison Wang out_8(&gpio->par_feci2c, 280aa0d99fcSAlison Wang GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA); 281a4145534SPeter Tyser #endif 282a4145534SPeter Tyser 283a4145534SPeter Tyser icache_enable(); 284a4145534SPeter Tyser } 285a4145534SPeter Tyser 286a4145534SPeter Tyser /* 287a4145534SPeter Tyser * initialize higher level parts of CPU like timers 288a4145534SPeter Tyser */ 289a4145534SPeter Tyser int cpu_init_r(void) 290a4145534SPeter Tyser { 291a4145534SPeter Tyser return (0); 292a4145534SPeter Tyser } 293a4145534SPeter Tyser 294a4145534SPeter Tyser void uart_port_conf(int port) 295a4145534SPeter Tyser { 296aa0d99fcSAlison Wang gpio_t *gpio = (gpio_t *) MMAP_GPIO; 297a4145534SPeter Tyser 298a4145534SPeter Tyser /* Setup Ports: */ 299a4145534SPeter Tyser switch (port) { 300a4145534SPeter Tyser case 0: 301aa0d99fcSAlison Wang clrbits_be16(&gpio->par_uart, 302aa0d99fcSAlison Wang GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0); 303aa0d99fcSAlison Wang setbits_be16(&gpio->par_uart, 304aa0d99fcSAlison Wang GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0); 305a4145534SPeter Tyser break; 306a4145534SPeter Tyser case 1: 307aa0d99fcSAlison Wang clrbits_be16(&gpio->par_uart, 308aa0d99fcSAlison Wang GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3)); 309aa0d99fcSAlison Wang setbits_be16(&gpio->par_uart, 310aa0d99fcSAlison Wang GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3)); 311a4145534SPeter Tyser break; 312a4145534SPeter Tyser case 2: 313a4145534SPeter Tyser #ifdef CONFIG_SYS_UART2_ALT1_GPIO 314aa0d99fcSAlison Wang clrbits_8(&gpio->par_timer, 0xf0); 315aa0d99fcSAlison Wang setbits_8(&gpio->par_timer, 316aa0d99fcSAlison Wang GPIO_PAR_TIN3_URXD2 | GPIO_PAR_TIN2_UTXD2); 317a4145534SPeter Tyser #elif defined(CONFIG_SYS_UART2_ALT2_GPIO) 318aa0d99fcSAlison Wang clrbits_8(&gpio->par_feci2c, 0x00ff); 319aa0d99fcSAlison Wang setbits_8(&gpio->par_feci2c, 320aa0d99fcSAlison Wang GPIO_PAR_FECI2C_SCL_UTXD2 | GPIO_PAR_FECI2C_SDA_URXD2); 321a4145534SPeter Tyser #elif defined(CONFIG_SYS_UART2_ALT3_GPIO) 322aa0d99fcSAlison Wang clrbits_be16(&gpio->par_ssi, 0x0f00); 323aa0d99fcSAlison Wang setbits_be16(&gpio->par_ssi, 324aa0d99fcSAlison Wang GPIO_PAR_SSI_RXD(2) | GPIO_PAR_SSI_TXD(2)); 325a4145534SPeter Tyser #endif 326a4145534SPeter Tyser break; 327a4145534SPeter Tyser } 328a4145534SPeter Tyser } 329a4145534SPeter Tyser 330a4145534SPeter Tyser #if defined(CONFIG_CMD_NET) 331a4145534SPeter Tyser int fecpin_setclear(struct eth_device *dev, int setclear) 332a4145534SPeter Tyser { 333aa0d99fcSAlison Wang gpio_t *gpio = (gpio_t *) MMAP_GPIO; 334a4145534SPeter Tyser 335a4145534SPeter Tyser if (setclear) { 336aa0d99fcSAlison Wang setbits_8(&gpio->par_fec, 337aa0d99fcSAlison Wang GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC); 338aa0d99fcSAlison Wang setbits_8(&gpio->par_feci2c, 339aa0d99fcSAlison Wang GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO); 340a4145534SPeter Tyser } else { 341aa0d99fcSAlison Wang clrbits_8(&gpio->par_fec, 342aa0d99fcSAlison Wang GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC); 343aa0d99fcSAlison Wang clrbits_8(&gpio->par_feci2c, 344aa0d99fcSAlison Wang GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO); 345a4145534SPeter Tyser } 346a4145534SPeter Tyser return 0; 347a4145534SPeter Tyser } 348a4145534SPeter Tyser #endif 349a4145534SPeter Tyser #endif /* CONFIG_MCF532x */ 350