1a4145534SPeter Tyser /* 2a4145534SPeter Tyser * 3a4145534SPeter Tyser * (C) Copyright 2000-2003 4a4145534SPeter Tyser * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5a4145534SPeter Tyser * 6aa0d99fcSAlison Wang * (C) Copyright 2004-2008, 2012 Freescale Semiconductor, Inc. 7a4145534SPeter Tyser * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 8a4145534SPeter Tyser * 9a4145534SPeter Tyser * See file CREDITS for list of people who contributed to this 10a4145534SPeter Tyser * project. 11a4145534SPeter Tyser * 12a4145534SPeter Tyser * This program is free software; you can redistribute it and/or 13a4145534SPeter Tyser * modify it under the terms of the GNU General Public License as 14a4145534SPeter Tyser * published by the Free Software Foundation; either version 2 of 15a4145534SPeter Tyser * the License, or (at your option) any later version. 16a4145534SPeter Tyser * 17a4145534SPeter Tyser * This program is distributed in the hope that it will be useful, 18a4145534SPeter Tyser * but WITHOUT ANY WARRANTY; without even the implied warranty of 19a4145534SPeter Tyser * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20a4145534SPeter Tyser * GNU General Public License for more details. 21a4145534SPeter Tyser * 22a4145534SPeter Tyser * You should have received a copy of the GNU General Public License 23a4145534SPeter Tyser * along with this program; if not, write to the Free Software 24a4145534SPeter Tyser * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25a4145534SPeter Tyser * MA 02111-1307 USA 26a4145534SPeter Tyser */ 27a4145534SPeter Tyser 28a4145534SPeter Tyser #include <common.h> 29a4145534SPeter Tyser #include <watchdog.h> 30a4145534SPeter Tyser #include <asm/immap.h> 31aa0d99fcSAlison Wang #include <asm/io.h> 32a4145534SPeter Tyser 33a4145534SPeter Tyser #if defined(CONFIG_CMD_NET) 34a4145534SPeter Tyser #include <config.h> 35a4145534SPeter Tyser #include <net.h> 36a4145534SPeter Tyser #include <asm/fec.h> 37a4145534SPeter Tyser #endif 38a4145534SPeter Tyser 39a4145534SPeter Tyser #ifdef CONFIG_MCF5301x 40a4145534SPeter Tyser void cpu_init_f(void) 41a4145534SPeter Tyser { 42aa0d99fcSAlison Wang scm1_t *scm1 = (scm1_t *) MMAP_SCM1; 43aa0d99fcSAlison Wang gpio_t *gpio = (gpio_t *) MMAP_GPIO; 44aa0d99fcSAlison Wang fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; 45a4145534SPeter Tyser 46aa0d99fcSAlison Wang out_be32(&scm1->mpr, 0x77777777); 47aa0d99fcSAlison Wang out_be32(&scm1->pacra, 0); 48aa0d99fcSAlison Wang out_be32(&scm1->pacrb, 0); 49aa0d99fcSAlison Wang out_be32(&scm1->pacrc, 0); 50aa0d99fcSAlison Wang out_be32(&scm1->pacrd, 0); 51aa0d99fcSAlison Wang out_be32(&scm1->pacre, 0); 52aa0d99fcSAlison Wang out_be32(&scm1->pacrf, 0); 53aa0d99fcSAlison Wang out_be32(&scm1->pacrg, 0); 54a4145534SPeter Tyser 55a4145534SPeter Tyser #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ 56a4145534SPeter Tyser && defined(CONFIG_SYS_CS0_CTRL)) 57aa0d99fcSAlison Wang setbits_8(&gpio->par_cs, GPIO_PAR_CS0_CS0); 58aa0d99fcSAlison Wang out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); 59aa0d99fcSAlison Wang out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); 60aa0d99fcSAlison Wang out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); 61a4145534SPeter Tyser #endif 62a4145534SPeter Tyser 63a4145534SPeter Tyser #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ 64a4145534SPeter Tyser && defined(CONFIG_SYS_CS1_CTRL)) 65aa0d99fcSAlison Wang setbits_8(&gpio->par_cs, GPIO_PAR_CS1_CS1); 66aa0d99fcSAlison Wang out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); 67aa0d99fcSAlison Wang out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); 68aa0d99fcSAlison Wang out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); 69a4145534SPeter Tyser #endif 70a4145534SPeter Tyser 71a4145534SPeter Tyser #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ 72a4145534SPeter Tyser && defined(CONFIG_SYS_CS2_CTRL)) 73aa0d99fcSAlison Wang out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); 74aa0d99fcSAlison Wang out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); 75aa0d99fcSAlison Wang out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); 76a4145534SPeter Tyser #endif 77a4145534SPeter Tyser 78a4145534SPeter Tyser #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ 79a4145534SPeter Tyser && defined(CONFIG_SYS_CS3_CTRL)) 80aa0d99fcSAlison Wang out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); 81aa0d99fcSAlison Wang out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); 82aa0d99fcSAlison Wang out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); 83a4145534SPeter Tyser #endif 84a4145534SPeter Tyser 85a4145534SPeter Tyser #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ 86a4145534SPeter Tyser && defined(CONFIG_SYS_CS4_CTRL)) 87aa0d99fcSAlison Wang setbits_8(&gpio->par_cs, GPIO_PAR_CS4); 88aa0d99fcSAlison Wang out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE); 89aa0d99fcSAlison Wang out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL); 90aa0d99fcSAlison Wang out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK); 91a4145534SPeter Tyser #endif 92a4145534SPeter Tyser 93a4145534SPeter Tyser #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \ 94a4145534SPeter Tyser && defined(CONFIG_SYS_CS5_CTRL)) 95aa0d99fcSAlison Wang setbits_8(&gpio->par_cs, GPIO_PAR_CS5); 96aa0d99fcSAlison Wang out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE); 97aa0d99fcSAlison Wang out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL); 98aa0d99fcSAlison Wang out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK); 99a4145534SPeter Tyser #endif 100a4145534SPeter Tyser 101*00f792e0SHeiko Schocher #ifdef CONFIG_SYS_I2C_FSL 102aa0d99fcSAlison Wang out_8(&gpio->par_feci2c, 103aa0d99fcSAlison Wang GPIO_PAR_FECI2C_SDA_SDA | GPIO_PAR_FECI2C_SCL_SCL); 104a4145534SPeter Tyser #endif 105a4145534SPeter Tyser 106a4145534SPeter Tyser icache_enable(); 107a4145534SPeter Tyser } 108a4145534SPeter Tyser 109a4145534SPeter Tyser /* initialize higher level parts of CPU like timers */ 110a4145534SPeter Tyser int cpu_init_r(void) 111a4145534SPeter Tyser { 112a4145534SPeter Tyser #ifdef CONFIG_MCFFEC 113aa0d99fcSAlison Wang ccm_t *ccm = (ccm_t *) MMAP_CCM; 114a4145534SPeter Tyser #endif 115a4145534SPeter Tyser #ifdef CONFIG_MCFRTC 116aa0d99fcSAlison Wang rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE); 117aa0d99fcSAlison Wang rtcex_t *rtcex = (rtcex_t *) &rtc->extended; 118a4145534SPeter Tyser 119aa0d99fcSAlison Wang out_be32(&rtcex->gocu, CONFIG_SYS_RTC_CNT); 120aa0d99fcSAlison Wang out_be32(&rtcex->gocl, CONFIG_SYS_RTC_SETUP); 121a4145534SPeter Tyser 122a4145534SPeter Tyser #endif 123a4145534SPeter Tyser #ifdef CONFIG_MCFFEC 124a4145534SPeter Tyser if (CONFIG_SYS_FEC0_MIIBASE != CONFIG_SYS_FEC1_MIIBASE) 125aa0d99fcSAlison Wang setbits_be16(&ccm->misccr, CCM_MISCCR_FECM); 126a4145534SPeter Tyser else 127aa0d99fcSAlison Wang clrbits_be16(&ccm->misccr, CCM_MISCCR_FECM); 128a4145534SPeter Tyser #endif 129a4145534SPeter Tyser 130a4145534SPeter Tyser return (0); 131a4145534SPeter Tyser } 132a4145534SPeter Tyser 133a4145534SPeter Tyser void uart_port_conf(int port) 134a4145534SPeter Tyser { 135aa0d99fcSAlison Wang gpio_t *gpio = (gpio_t *) MMAP_GPIO; 136a4145534SPeter Tyser 137a4145534SPeter Tyser /* Setup Ports: */ 138a4145534SPeter Tyser switch (port) { 139a4145534SPeter Tyser case 0: 140aa0d99fcSAlison Wang clrbits_8(&gpio->par_uart, 141aa0d99fcSAlison Wang GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD); 142aa0d99fcSAlison Wang setbits_8(&gpio->par_uart, 143aa0d99fcSAlison Wang GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD); 144a4145534SPeter Tyser break; 145a4145534SPeter Tyser case 1: 146a4145534SPeter Tyser #ifdef CONFIG_SYS_UART1_ALT1_GPIO 147aa0d99fcSAlison Wang clrbits_8(&gpio->par_simp1h, 148aa0d99fcSAlison Wang GPIO_PAR_SIMP1H_DATA1_UNMASK | 149a4145534SPeter Tyser GPIO_PAR_SIMP1H_VEN1_UNMASK); 150aa0d99fcSAlison Wang setbits_8(&gpio->par_simp1h, 151aa0d99fcSAlison Wang GPIO_PAR_SIMP1H_DATA1_U1TXD | 152aa0d99fcSAlison Wang GPIO_PAR_SIMP1H_VEN1_U1RXD); 153a4145534SPeter Tyser #elif defined(CONFIG_SYS_UART1_ALT2_GPIO) 154aa0d99fcSAlison Wang clrbits_8(&gpio->par_ssih, 155aa0d99fcSAlison Wang GPIO_PAR_SSIH_RXD_UNMASK | 156aa0d99fcSAlison Wang GPIO_PAR_SSIH_TXD_UNMASK); 157aa0d99fcSAlison Wang setbits_8(&gpio->par_ssih, 158aa0d99fcSAlison Wang GPIO_PAR_SSIH_RXD_U1RXD | 159aa0d99fcSAlison Wang GPIO_PAR_SSIH_TXD_U1TXD); 160a4145534SPeter Tyser #endif 161a4145534SPeter Tyser break; 162a4145534SPeter Tyser case 2: 163a4145534SPeter Tyser #ifdef CONFIG_SYS_UART2_PRI_GPIO 164aa0d99fcSAlison Wang setbits_8(&gpio->par_uart, 165aa0d99fcSAlison Wang GPIO_PAR_UART_U2TXD | 166aa0d99fcSAlison Wang GPIO_PAR_UART_U2RXD); 167a4145534SPeter Tyser #elif defined(CONFIG_SYS_UART2_ALT1_GPIO) 168aa0d99fcSAlison Wang clrbits_8(&gpio->par_dspih, 169aa0d99fcSAlison Wang GPIO_PAR_DSPIH_SIN_UNMASK | 170aa0d99fcSAlison Wang GPIO_PAR_DSPIH_SOUT_UNMASK); 171aa0d99fcSAlison Wang setbits_8(&gpio->par_dspih, 172aa0d99fcSAlison Wang GPIO_PAR_DSPIH_SIN_U2RXD | 173aa0d99fcSAlison Wang GPIO_PAR_DSPIH_SOUT_U2TXD); 174a4145534SPeter Tyser #elif defined(CONFIG_SYS_UART2_ALT2_GPIO) 175aa0d99fcSAlison Wang clrbits_8(&gpio->par_feci2c, 176aa0d99fcSAlison Wang GPIO_PAR_FECI2C_SDA_UNMASK | 177aa0d99fcSAlison Wang GPIO_PAR_FECI2C_SCL_UNMASK); 178aa0d99fcSAlison Wang setbits_8(&gpio->par_feci2c, 179aa0d99fcSAlison Wang GPIO_PAR_FECI2C_SDA_U2TXD | 180aa0d99fcSAlison Wang GPIO_PAR_FECI2C_SCL_U2RXD); 181a4145534SPeter Tyser #endif 182a4145534SPeter Tyser break; 183a4145534SPeter Tyser } 184a4145534SPeter Tyser } 185a4145534SPeter Tyser 186a4145534SPeter Tyser #if defined(CONFIG_CMD_NET) 187a4145534SPeter Tyser int fecpin_setclear(struct eth_device *dev, int setclear) 188a4145534SPeter Tyser { 189aa0d99fcSAlison Wang gpio_t *gpio = (gpio_t *) MMAP_GPIO; 190a4145534SPeter Tyser struct fec_info_s *info = (struct fec_info_s *)dev->priv; 191a4145534SPeter Tyser 192a4145534SPeter Tyser if (setclear) { 193a4145534SPeter Tyser if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { 194aa0d99fcSAlison Wang setbits_8(&gpio->par_fec, 195aa0d99fcSAlison Wang GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC); 196aa0d99fcSAlison Wang setbits_8(&gpio->par_feci2c, 197aa0d99fcSAlison Wang GPIO_PAR_FECI2C_MDC0 | GPIO_PAR_FECI2C_MDIO0); 198a4145534SPeter Tyser } else { 199aa0d99fcSAlison Wang setbits_8(&gpio->par_fec, 200aa0d99fcSAlison Wang GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC); 201aa0d99fcSAlison Wang setbits_8(&gpio->par_feci2c, 202aa0d99fcSAlison Wang GPIO_PAR_FECI2C_MDC1 | GPIO_PAR_FECI2C_MDIO1); 203a4145534SPeter Tyser } 204a4145534SPeter Tyser } else { 205a4145534SPeter Tyser if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { 206aa0d99fcSAlison Wang clrbits_8(&gpio->par_fec, 207aa0d99fcSAlison Wang GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC); 208aa0d99fcSAlison Wang clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII0_UNMASK); 209a4145534SPeter Tyser } else { 210aa0d99fcSAlison Wang clrbits_8(&gpio->par_fec, 211aa0d99fcSAlison Wang GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC); 212aa0d99fcSAlison Wang clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII1_UNMASK); 213a4145534SPeter Tyser } 214a4145534SPeter Tyser } 215a4145534SPeter Tyser return 0; 216a4145534SPeter Tyser } 217a4145534SPeter Tyser #endif /* CONFIG_CMD_NET */ 218a4145534SPeter Tyser #endif /* CONFIG_MCF5301x */ 219a4145534SPeter Tyser 220a4145534SPeter Tyser #ifdef CONFIG_MCF532x 221a4145534SPeter Tyser void cpu_init_f(void) 222a4145534SPeter Tyser { 223aa0d99fcSAlison Wang scm1_t *scm1 = (scm1_t *) MMAP_SCM1; 224aa0d99fcSAlison Wang scm2_t *scm2 = (scm2_t *) MMAP_SCM2; 225aa0d99fcSAlison Wang gpio_t *gpio = (gpio_t *) MMAP_GPIO; 226aa0d99fcSAlison Wang fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; 227aa0d99fcSAlison Wang wdog_t *wdog = (wdog_t *) MMAP_WDOG; 228a4145534SPeter Tyser 229a4145534SPeter Tyser /* watchdog is enabled by default - disable the watchdog */ 230a4145534SPeter Tyser #ifndef CONFIG_WATCHDOG 231aa0d99fcSAlison Wang out_be16(&wdog->cr, 0); 232a4145534SPeter Tyser #endif 233a4145534SPeter Tyser 234aa0d99fcSAlison Wang out_be32(&scm1->mpr0, 0x77777777); 235aa0d99fcSAlison Wang out_be32(&scm2->pacra, 0); 236aa0d99fcSAlison Wang out_be32(&scm2->pacrb, 0); 237aa0d99fcSAlison Wang out_be32(&scm2->pacrc, 0); 238aa0d99fcSAlison Wang out_be32(&scm2->pacrd, 0); 239aa0d99fcSAlison Wang out_be32(&scm2->pacre, 0); 240aa0d99fcSAlison Wang out_be32(&scm2->pacrf, 0); 241aa0d99fcSAlison Wang out_be32(&scm2->pacrg, 0); 242aa0d99fcSAlison Wang out_be32(&scm1->pacrh, 0); 243a4145534SPeter Tyser 244a4145534SPeter Tyser /* Port configuration */ 245aa0d99fcSAlison Wang out_8(&gpio->par_cs, 0); 246a4145534SPeter Tyser 247a4145534SPeter Tyser #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ 248a4145534SPeter Tyser && defined(CONFIG_SYS_CS0_CTRL)) 249aa0d99fcSAlison Wang out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); 250aa0d99fcSAlison Wang out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); 251aa0d99fcSAlison Wang out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); 252a4145534SPeter Tyser #endif 253a4145534SPeter Tyser 254a4145534SPeter Tyser #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ 255a4145534SPeter Tyser && defined(CONFIG_SYS_CS1_CTRL)) 256a4145534SPeter Tyser /* Latch chipselect */ 257aa0d99fcSAlison Wang setbits_8(&gpio->par_cs, GPIO_PAR_CS1); 258aa0d99fcSAlison Wang out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); 259aa0d99fcSAlison Wang out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); 260aa0d99fcSAlison Wang out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); 261a4145534SPeter Tyser #endif 262a4145534SPeter Tyser 263a4145534SPeter Tyser #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ 264a4145534SPeter Tyser && defined(CONFIG_SYS_CS2_CTRL)) 265aa0d99fcSAlison Wang setbits_8(&gpio->par_cs, GPIO_PAR_CS2); 266aa0d99fcSAlison Wang out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); 267aa0d99fcSAlison Wang out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); 268aa0d99fcSAlison Wang out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); 269a4145534SPeter Tyser #endif 270a4145534SPeter Tyser 271a4145534SPeter Tyser #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ 272a4145534SPeter Tyser && defined(CONFIG_SYS_CS3_CTRL)) 273aa0d99fcSAlison Wang setbits_8(&gpio->par_cs, GPIO_PAR_CS3); 274aa0d99fcSAlison Wang out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); 275aa0d99fcSAlison Wang out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); 276aa0d99fcSAlison Wang out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); 277a4145534SPeter Tyser #endif 278a4145534SPeter Tyser 279a4145534SPeter Tyser #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ 280a4145534SPeter Tyser && defined(CONFIG_SYS_CS4_CTRL)) 281aa0d99fcSAlison Wang setbits_8(&gpio->par_cs, GPIO_PAR_CS4); 282aa0d99fcSAlison Wang out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE); 283aa0d99fcSAlison Wang out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL); 284aa0d99fcSAlison Wang out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK); 285a4145534SPeter Tyser #endif 286a4145534SPeter Tyser 287a4145534SPeter Tyser #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \ 288a4145534SPeter Tyser && defined(CONFIG_SYS_CS5_CTRL)) 289aa0d99fcSAlison Wang setbits_8(&gpio->par_cs, GPIO_PAR_CS5); 290aa0d99fcSAlison Wang out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE); 291aa0d99fcSAlison Wang out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL); 292aa0d99fcSAlison Wang out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK); 293a4145534SPeter Tyser #endif 294a4145534SPeter Tyser 295*00f792e0SHeiko Schocher #ifdef CONFIG_SYS_I2C_FSL 296aa0d99fcSAlison Wang out_8(&gpio->par_feci2c, 297aa0d99fcSAlison Wang GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA); 298a4145534SPeter Tyser #endif 299a4145534SPeter Tyser 300a4145534SPeter Tyser icache_enable(); 301a4145534SPeter Tyser } 302a4145534SPeter Tyser 303a4145534SPeter Tyser /* 304a4145534SPeter Tyser * initialize higher level parts of CPU like timers 305a4145534SPeter Tyser */ 306a4145534SPeter Tyser int cpu_init_r(void) 307a4145534SPeter Tyser { 308a4145534SPeter Tyser return (0); 309a4145534SPeter Tyser } 310a4145534SPeter Tyser 311a4145534SPeter Tyser void uart_port_conf(int port) 312a4145534SPeter Tyser { 313aa0d99fcSAlison Wang gpio_t *gpio = (gpio_t *) MMAP_GPIO; 314a4145534SPeter Tyser 315a4145534SPeter Tyser /* Setup Ports: */ 316a4145534SPeter Tyser switch (port) { 317a4145534SPeter Tyser case 0: 318aa0d99fcSAlison Wang clrbits_be16(&gpio->par_uart, 319aa0d99fcSAlison Wang GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0); 320aa0d99fcSAlison Wang setbits_be16(&gpio->par_uart, 321aa0d99fcSAlison Wang GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0); 322a4145534SPeter Tyser break; 323a4145534SPeter Tyser case 1: 324aa0d99fcSAlison Wang clrbits_be16(&gpio->par_uart, 325aa0d99fcSAlison Wang GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3)); 326aa0d99fcSAlison Wang setbits_be16(&gpio->par_uart, 327aa0d99fcSAlison Wang GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3)); 328a4145534SPeter Tyser break; 329a4145534SPeter Tyser case 2: 330a4145534SPeter Tyser #ifdef CONFIG_SYS_UART2_ALT1_GPIO 331aa0d99fcSAlison Wang clrbits_8(&gpio->par_timer, 0xf0); 332aa0d99fcSAlison Wang setbits_8(&gpio->par_timer, 333aa0d99fcSAlison Wang GPIO_PAR_TIN3_URXD2 | GPIO_PAR_TIN2_UTXD2); 334a4145534SPeter Tyser #elif defined(CONFIG_SYS_UART2_ALT2_GPIO) 335aa0d99fcSAlison Wang clrbits_8(&gpio->par_feci2c, 0x00ff); 336aa0d99fcSAlison Wang setbits_8(&gpio->par_feci2c, 337aa0d99fcSAlison Wang GPIO_PAR_FECI2C_SCL_UTXD2 | GPIO_PAR_FECI2C_SDA_URXD2); 338a4145534SPeter Tyser #elif defined(CONFIG_SYS_UART2_ALT3_GPIO) 339aa0d99fcSAlison Wang clrbits_be16(&gpio->par_ssi, 0x0f00); 340aa0d99fcSAlison Wang setbits_be16(&gpio->par_ssi, 341aa0d99fcSAlison Wang GPIO_PAR_SSI_RXD(2) | GPIO_PAR_SSI_TXD(2)); 342a4145534SPeter Tyser #endif 343a4145534SPeter Tyser break; 344a4145534SPeter Tyser } 345a4145534SPeter Tyser } 346a4145534SPeter Tyser 347a4145534SPeter Tyser #if defined(CONFIG_CMD_NET) 348a4145534SPeter Tyser int fecpin_setclear(struct eth_device *dev, int setclear) 349a4145534SPeter Tyser { 350aa0d99fcSAlison Wang gpio_t *gpio = (gpio_t *) MMAP_GPIO; 351a4145534SPeter Tyser 352a4145534SPeter Tyser if (setclear) { 353aa0d99fcSAlison Wang setbits_8(&gpio->par_fec, 354aa0d99fcSAlison Wang GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC); 355aa0d99fcSAlison Wang setbits_8(&gpio->par_feci2c, 356aa0d99fcSAlison Wang GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO); 357a4145534SPeter Tyser } else { 358aa0d99fcSAlison Wang clrbits_8(&gpio->par_fec, 359aa0d99fcSAlison Wang GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC); 360aa0d99fcSAlison Wang clrbits_8(&gpio->par_feci2c, 361aa0d99fcSAlison Wang GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO); 362a4145534SPeter Tyser } 363a4145534SPeter Tyser return 0; 364a4145534SPeter Tyser } 365a4145534SPeter Tyser #endif 366a4145534SPeter Tyser #endif /* CONFIG_MCF532x */ 367