1 /* 2 * (C) Copyright 2000-2004 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 7 * 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * MA 02111-1307 USA 25 */ 26 27 #include <common.h> 28 #include <watchdog.h> 29 #include <asm/processor.h> 30 #include <asm/immap.h> 31 #include <asm/io.h> 32 33 #ifdef CONFIG_M5272 34 int interrupt_init(void) 35 { 36 intctrl_t *intp = (intctrl_t *) (MMAP_INTC); 37 38 /* disable all external interrupts */ 39 out_be32(&intp->int_icr1, 0x88888888); 40 out_be32(&intp->int_icr2, 0x88888888); 41 out_be32(&intp->int_icr3, 0x88888888); 42 out_be32(&intp->int_icr4, 0x88888888); 43 out_be32(&intp->int_pitr, 0x00000000); 44 45 /* initialize vector register */ 46 out_8(&intp->int_pivr, 0x40); 47 48 enable_interrupts(); 49 50 return 0; 51 } 52 53 #if defined(CONFIG_MCFTMR) 54 void dtimer_intr_setup(void) 55 { 56 intctrl_t *intp = (intctrl_t *) (CONFIG_SYS_INTR_BASE); 57 58 clrbits_be32(&intp->int_icr1, INT_ICR1_TMR3MASK); 59 setbits_be32(&intp->int_icr1, CONFIG_SYS_TMRINTR_PRI); 60 } 61 #endif /* CONFIG_MCFTMR */ 62 #endif /* CONFIG_M5272 */ 63 64 #if defined(CONFIG_M5208) || defined(CONFIG_M5282) || \ 65 defined(CONFIG_M5271) || defined(CONFIG_M5275) 66 int interrupt_init(void) 67 { 68 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); 69 70 /* Make sure all interrupts are disabled */ 71 #if defined(CONFIG_M5208) 72 out_be32(&intp->imrl0, 0xffffffff); 73 out_be32(&intp->imrh0, 0xffffffff); 74 #else 75 setbits_be32(&intp->imrl0, 0x1); 76 #endif 77 78 enable_interrupts(); 79 return 0; 80 } 81 82 #if defined(CONFIG_MCFTMR) 83 void dtimer_intr_setup(void) 84 { 85 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); 86 87 out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); 88 clrbits_be32(&intp->imrl0, 0x00000001); 89 clrbits_be32(&intp->imrl0, CONFIG_SYS_TMRINTR_MASK); 90 } 91 #endif /* CONFIG_MCFTMR */ 92 #endif /* CONFIG_M5282 | CONFIG_M5271 | CONFIG_M5275 */ 93 94 #if defined(CONFIG_M5249) || defined(CONFIG_M5253) 95 int interrupt_init(void) 96 { 97 enable_interrupts(); 98 99 return 0; 100 } 101 102 #if defined(CONFIG_MCFTMR) 103 void dtimer_intr_setup(void) 104 { 105 mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400); 106 mbar_writeByte(MCFSIM_TIMER2ICR, CONFIG_SYS_TMRINTR_PRI); 107 } 108 #endif /* CONFIG_MCFTMR */ 109 #endif /* CONFIG_M5249 || CONFIG_M5253 */ 110