1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2003 4 * Josef Baumgartner <josef.baumgartner@telex.de> 5 * 6 * MCF5282 additionals 7 * (C) Copyright 2005 8 * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de> 9 * (c) Copyright 2010 10 * Arcturus Networks Inc. <www.arcturusnetworks.com> 11 * 12 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. 13 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 14 * Hayden Fraser (Hayden.Fraser@freescale.com) 15 * 16 * MCF5275 additions 17 * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com) 18 */ 19 20 #include <common.h> 21 #include <watchdog.h> 22 #include <asm/immap.h> 23 #include <asm/io.h> 24 25 #if defined(CONFIG_CMD_NET) 26 #include <config.h> 27 #include <net.h> 28 #include <asm/fec.h> 29 #endif 30 31 #ifndef CONFIG_M5272 32 /* Only 5272 Flexbus chipselect is different from the rest */ 33 void init_fbcs(void) 34 { 35 fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS); 36 37 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ 38 && defined(CONFIG_SYS_CS0_CTRL)) 39 out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); 40 out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); 41 out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); 42 #else 43 #warning "Chip Select 0 are not initialized/used" 44 #endif 45 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ 46 && defined(CONFIG_SYS_CS1_CTRL)) 47 out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); 48 out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); 49 out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); 50 #endif 51 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ 52 && defined(CONFIG_SYS_CS2_CTRL)) 53 out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); 54 out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); 55 out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); 56 #endif 57 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ 58 && defined(CONFIG_SYS_CS3_CTRL)) 59 out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); 60 out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); 61 out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); 62 #endif 63 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ 64 && defined(CONFIG_SYS_CS4_CTRL)) 65 out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE); 66 out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL); 67 out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK); 68 #endif 69 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \ 70 && defined(CONFIG_SYS_CS5_CTRL)) 71 out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE); 72 out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL); 73 out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK); 74 #endif 75 #if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) \ 76 && defined(CONFIG_SYS_CS6_CTRL)) 77 out_be32(&fbcs->csar6, CONFIG_SYS_CS6_BASE); 78 out_be32(&fbcs->cscr6, CONFIG_SYS_CS6_CTRL); 79 out_be32(&fbcs->csmr6, CONFIG_SYS_CS6_MASK); 80 #endif 81 #if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) \ 82 && defined(CONFIG_SYS_CS7_CTRL)) 83 out_be32(&fbcs->csar7, CONFIG_SYS_CS7_BASE); 84 out_be32(&fbcs->cscr7, CONFIG_SYS_CS7_CTRL); 85 out_be32(&fbcs->csmr7, CONFIG_SYS_CS7_MASK); 86 #endif 87 } 88 #endif 89 90 #if defined(CONFIG_M5208) 91 void cpu_init_f(void) 92 { 93 scm1_t *scm1 = (scm1_t *) MMAP_SCM1; 94 95 #ifndef CONFIG_WATCHDOG 96 wdog_t *wdg = (wdog_t *) MMAP_WDOG; 97 98 /* Disable the watchdog if we aren't using it */ 99 out_be16(&wdg->cr, 0); 100 #endif 101 102 out_be32(&scm1->mpr, 0x77777777); 103 out_be32(&scm1->pacra, 0); 104 out_be32(&scm1->pacrb, 0); 105 out_be32(&scm1->pacrc, 0); 106 out_be32(&scm1->pacrd, 0); 107 out_be32(&scm1->pacre, 0); 108 out_be32(&scm1->pacrf, 0); 109 110 /* FlexBus Chipselect */ 111 init_fbcs(); 112 113 icache_enable(); 114 } 115 116 /* initialize higher level parts of CPU like timers */ 117 int cpu_init_r(void) 118 { 119 return (0); 120 } 121 122 void uart_port_conf(int port) 123 { 124 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 125 126 /* Setup Ports: */ 127 switch (port) { 128 case 0: 129 clrbits_be16(&gpio->par_uart, ~GPIO_PAR_UART0_UNMASK); 130 setbits_be16(&gpio->par_uart, GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD); 131 break; 132 case 1: 133 clrbits_be16(&gpio->par_uart, ~GPIO_PAR_UART0_UNMASK); 134 setbits_be16(&gpio->par_uart, GPIO_PAR_UART_U1TXD | GPIO_PAR_UART_U1RXD); 135 break; 136 case 2: 137 #ifdef CONFIG_SYS_UART2_PRI_GPIO 138 clrbits_8(&gpio->par_timer, 139 ~(GPIO_PAR_TMR_TIN0_UNMASK | GPIO_PAR_TMR_TIN1_UNMASK)); 140 setbits_8(&gpio->par_timer, 141 GPIO_PAR_TMR_TIN0_U2TXD | GPIO_PAR_TMR_TIN1_U2RXD); 142 #endif 143 #ifdef CONFIG_SYS_UART2_ALT1_GPIO 144 clrbits_8(&gpio->par_feci2c, 145 ~(GPIO_PAR_FECI2C_MDC_UNMASK | GPIO_PAR_FECI2C_MDIO_UNMASK)); 146 setbits_8(&gpio->par_feci2c, 147 GPIO_PAR_FECI2C_MDC_U2TXD | GPIO_PAR_FECI2C_MDIO_U2RXD); 148 #endif 149 #ifdef CONFIG_SYS_UART2_ALT1_GPIO 150 clrbits_8(&gpio->par_feci2c, 151 ~(GPIO_PAR_FECI2C_SDA_UNMASK | GPIO_PAR_FECI2C_SCL_UNMASK)); 152 setbits_8(&gpio->par_feci2c, 153 GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD); 154 #endif 155 break; 156 } 157 } 158 159 #if defined(CONFIG_CMD_NET) 160 int fecpin_setclear(struct eth_device *dev, int setclear) 161 { 162 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 163 164 if (setclear) { 165 setbits_8(&gpio->par_fec, 166 GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC); 167 setbits_8(&gpio->par_feci2c, 168 GPIO_PAR_FECI2C_MDC_MDC | GPIO_PAR_FECI2C_MDIO_MDIO); 169 } else { 170 clrbits_8(&gpio->par_fec, 171 ~(GPIO_PAR_FEC_7W_UNMASK & GPIO_PAR_FEC_MII_UNMASK)); 172 clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII_UNMASK); 173 } 174 return 0; 175 } 176 #endif /* CONFIG_CMD_NET */ 177 #endif /* CONFIG_M5208 */ 178 179 #if defined(CONFIG_M5253) 180 /* 181 * Breath some life into the CPU... 182 * 183 * Set up the memory map, 184 * initialize a bunch of registers, 185 * initialize the UPM's 186 */ 187 void cpu_init_f(void) 188 { 189 mbar_writeByte(MCFSIM_MPARK, 0x40); /* 5249 Internal Core takes priority over DMA */ 190 mbar_writeByte(MCFSIM_SYPCR, 0x00); 191 mbar_writeByte(MCFSIM_SWIVR, 0x0f); 192 mbar_writeByte(MCFSIM_SWSR, 0x00); 193 mbar_writeByte(MCFSIM_SWDICR, 0x00); 194 mbar_writeByte(MCFSIM_TIMER1ICR, 0x00); 195 mbar_writeByte(MCFSIM_TIMER2ICR, 0x88); 196 mbar_writeByte(MCFSIM_I2CICR, 0x00); 197 mbar_writeByte(MCFSIM_UART1ICR, 0x00); 198 mbar_writeByte(MCFSIM_UART2ICR, 0x00); 199 mbar_writeByte(MCFSIM_ICR6, 0x00); 200 mbar_writeByte(MCFSIM_ICR7, 0x00); 201 mbar_writeByte(MCFSIM_ICR8, 0x00); 202 mbar_writeByte(MCFSIM_ICR9, 0x00); 203 mbar_writeByte(MCFSIM_QSPIICR, 0x00); 204 205 mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080); 206 mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */ 207 mbar2_writeByte(MCFSIM_SPURVEC, 0x00); 208 209 /*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */ 210 211 /* FlexBus Chipselect */ 212 init_fbcs(); 213 214 #ifdef CONFIG_SYS_I2C_FSL 215 CONFIG_SYS_I2C_PINMUX_REG = 216 CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR; 217 CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET; 218 #ifdef CONFIG_SYS_I2C2_OFFSET 219 CONFIG_SYS_I2C2_PINMUX_REG &= CONFIG_SYS_I2C2_PINMUX_CLR; 220 CONFIG_SYS_I2C2_PINMUX_REG |= CONFIG_SYS_I2C2_PINMUX_SET; 221 #endif 222 #endif 223 224 /* enable instruction cache now */ 225 icache_enable(); 226 } 227 228 /*initialize higher level parts of CPU like timers */ 229 int cpu_init_r(void) 230 { 231 return (0); 232 } 233 234 void uart_port_conf(int port) 235 { 236 u32 *par = (u32 *) MMAP_PAR; 237 238 /* Setup Ports: */ 239 switch (port) { 240 case 1: 241 clrbits_be32(par, 0x00180000); 242 setbits_be32(par, 0x00180000); 243 break; 244 case 2: 245 clrbits_be32(par, 0x00000003); 246 clrbits_be32(par, 0xFFFFFFFC); 247 break; 248 } 249 } 250 #endif /* #if defined(CONFIG_M5253) */ 251 252 #if defined(CONFIG_M5271) 253 void cpu_init_f(void) 254 { 255 #ifndef CONFIG_WATCHDOG 256 /* Disable the watchdog if we aren't using it */ 257 mbar_writeShort(MCF_WTM_WCR, 0); 258 #endif 259 260 /* FlexBus Chipselect */ 261 init_fbcs(); 262 263 #ifdef CONFIG_SYS_MCF_SYNCR 264 /* Set clockspeed according to board header file */ 265 mbar_writeLong(MCF_FMPLL_SYNCR, CONFIG_SYS_MCF_SYNCR); 266 #else 267 /* Set clockspeed to 100MHz */ 268 mbar_writeLong(MCF_FMPLL_SYNCR, 269 MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0)); 270 #endif 271 while (!(mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK)) ; 272 } 273 274 /* 275 * initialize higher level parts of CPU like timers 276 */ 277 int cpu_init_r(void) 278 { 279 return (0); 280 } 281 282 void uart_port_conf(int port) 283 { 284 u16 temp; 285 286 /* Setup Ports: */ 287 switch (port) { 288 case 0: 289 temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xFFF3; 290 temp |= (MCF_GPIO_PAR_UART_U0TXD | MCF_GPIO_PAR_UART_U0RXD); 291 mbar_writeShort(MCF_GPIO_PAR_UART, temp); 292 break; 293 case 1: 294 temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xF0FF; 295 temp |= (MCF_GPIO_PAR_UART_U1RXD_UART1 | MCF_GPIO_PAR_UART_U1TXD_UART1); 296 mbar_writeShort(MCF_GPIO_PAR_UART, temp); 297 break; 298 case 2: 299 temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xCFFF; 300 temp |= (0x3000); 301 mbar_writeShort(MCF_GPIO_PAR_UART, temp); 302 break; 303 } 304 } 305 306 #if defined(CONFIG_CMD_NET) 307 int fecpin_setclear(struct eth_device *dev, int setclear) 308 { 309 if (setclear) { 310 /* Enable Ethernet pins */ 311 mbar_writeByte(MCF_GPIO_PAR_FECI2C, 312 (mbar_readByte(MCF_GPIO_PAR_FECI2C) | 0xF0)); 313 } else { 314 } 315 316 return 0; 317 } 318 #endif /* CONFIG_CMD_NET */ 319 320 #endif /* CONFIG_M5271 */ 321 322 #if defined(CONFIG_M5272) 323 /* 324 * Breath some life into the CPU... 325 * 326 * Set up the memory map, 327 * initialize a bunch of registers, 328 * initialize the UPM's 329 */ 330 void cpu_init_f(void) 331 { 332 /* if we come from RAM we assume the CPU is 333 * already initialized. 334 */ 335 #ifndef CONFIG_MONITOR_IS_IN_RAM 336 sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR); 337 gpio_t *gpio = (gpio_t *) (MMAP_GPIO); 338 csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS); 339 340 out_be16(&sysctrl->sc_scr, CONFIG_SYS_SCR); 341 out_be16(&sysctrl->sc_spr, CONFIG_SYS_SPR); 342 343 /* Setup Ports: */ 344 out_be32(&gpio->gpio_pacnt, CONFIG_SYS_PACNT); 345 out_be16(&gpio->gpio_paddr, CONFIG_SYS_PADDR); 346 out_be16(&gpio->gpio_padat, CONFIG_SYS_PADAT); 347 out_be32(&gpio->gpio_pbcnt, CONFIG_SYS_PBCNT); 348 out_be16(&gpio->gpio_pbddr, CONFIG_SYS_PBDDR); 349 out_be16(&gpio->gpio_pbdat, CONFIG_SYS_PBDAT); 350 out_be32(&gpio->gpio_pdcnt, CONFIG_SYS_PDCNT); 351 352 /* Memory Controller: */ 353 out_be32(&csctrl->cs_br0, CONFIG_SYS_BR0_PRELIM); 354 out_be32(&csctrl->cs_or0, CONFIG_SYS_OR0_PRELIM); 355 356 #if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM)) 357 out_be32(&csctrl->cs_br1, CONFIG_SYS_BR1_PRELIM); 358 out_be32(&csctrl->cs_or1, CONFIG_SYS_OR1_PRELIM); 359 #endif 360 361 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) 362 out_be32(&csctrl->cs_br2, CONFIG_SYS_BR2_PRELIM); 363 out_be32(&csctrl->cs_or2, CONFIG_SYS_OR2_PRELIM); 364 #endif 365 366 #if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM) 367 out_be32(&csctrl->cs_br3, CONFIG_SYS_BR3_PRELIM); 368 out_be32(&csctrl->cs_or3, CONFIG_SYS_OR3_PRELIM); 369 #endif 370 371 #if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM) 372 out_be32(&csctrl->cs_br4, CONFIG_SYS_BR4_PRELIM); 373 out_be32(&csctrl->cs_or4, CONFIG_SYS_OR4_PRELIM); 374 #endif 375 376 #if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM) 377 out_be32(&csctrl->cs_br5, CONFIG_SYS_BR5_PRELIM); 378 out_be32(&csctrl->cs_or5, CONFIG_SYS_OR5_PRELIM); 379 #endif 380 381 #if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM) 382 out_be32(&csctrl->cs_br6, CONFIG_SYS_BR6_PRELIM); 383 out_be32(&csctrl->cs_or6, CONFIG_SYS_OR6_PRELIM); 384 #endif 385 386 #if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM) 387 out_be32(&csctrl->cs_br7, CONFIG_SYS_BR7_PRELIM); 388 out_be32(&csctrl->cs_or7, CONFIG_SYS_OR7_PRELIM); 389 #endif 390 391 #endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */ 392 393 /* enable instruction cache now */ 394 icache_enable(); 395 396 } 397 398 /* 399 * initialize higher level parts of CPU like timers 400 */ 401 int cpu_init_r(void) 402 { 403 return (0); 404 } 405 406 void uart_port_conf(int port) 407 { 408 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 409 410 /* Setup Ports: */ 411 switch (port) { 412 case 0: 413 clrbits_be32(&gpio->gpio_pbcnt, 414 GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK); 415 setbits_be32(&gpio->gpio_pbcnt, 416 GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD); 417 break; 418 case 1: 419 clrbits_be32(&gpio->gpio_pdcnt, 420 GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK); 421 setbits_be32(&gpio->gpio_pdcnt, 422 GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD); 423 break; 424 } 425 } 426 427 #if defined(CONFIG_CMD_NET) 428 int fecpin_setclear(struct eth_device *dev, int setclear) 429 { 430 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 431 432 if (setclear) { 433 setbits_be32(&gpio->gpio_pbcnt, 434 GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER | 435 GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 | 436 GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 | 437 GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3); 438 } else { 439 } 440 return 0; 441 } 442 #endif /* CONFIG_CMD_NET */ 443 #endif /* #if defined(CONFIG_M5272) */ 444 445 #if defined(CONFIG_M5275) 446 447 /* 448 * Breathe some life into the CPU... 449 * 450 * Set up the memory map, 451 * initialize a bunch of registers, 452 * initialize the UPM's 453 */ 454 void cpu_init_f(void) 455 { 456 /* 457 * if we come from RAM we assume the CPU is 458 * already initialized. 459 */ 460 461 #ifndef CONFIG_MONITOR_IS_IN_RAM 462 wdog_t *wdog_reg = (wdog_t *) (MMAP_WDOG); 463 gpio_t *gpio_reg = (gpio_t *) (MMAP_GPIO); 464 465 /* Kill watchdog so we can initialize the PLL */ 466 out_be16(&wdog_reg->wcr, 0); 467 468 /* FlexBus Chipselect */ 469 init_fbcs(); 470 #endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */ 471 472 #ifdef CONFIG_SYS_I2C_FSL 473 CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR; 474 CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET; 475 #endif 476 477 /* enable instruction cache now */ 478 icache_enable(); 479 } 480 481 /* 482 * initialize higher level parts of CPU like timers 483 */ 484 int cpu_init_r(void) 485 { 486 return (0); 487 } 488 489 void uart_port_conf(int port) 490 { 491 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 492 493 /* Setup Ports: */ 494 switch (port) { 495 case 0: 496 clrbits_be16(&gpio->par_uart, UART0_ENABLE_MASK); 497 setbits_be16(&gpio->par_uart, UART0_ENABLE_MASK); 498 break; 499 case 1: 500 clrbits_be16(&gpio->par_uart, UART1_ENABLE_MASK); 501 setbits_be16(&gpio->par_uart, UART1_ENABLE_MASK); 502 break; 503 case 2: 504 clrbits_be16(&gpio->par_uart, UART2_ENABLE_MASK); 505 setbits_be16(&gpio->par_uart, UART2_ENABLE_MASK); 506 break; 507 } 508 } 509 510 #if defined(CONFIG_CMD_NET) 511 int fecpin_setclear(struct eth_device *dev, int setclear) 512 { 513 struct fec_info_s *info = (struct fec_info_s *) dev->priv; 514 gpio_t *gpio = (gpio_t *)MMAP_GPIO; 515 516 if (setclear) { 517 /* Enable Ethernet pins */ 518 if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { 519 setbits_be16(&gpio->par_feci2c, 0x0f00); 520 setbits_8(&gpio->par_fec0hl, 0xc0); 521 } else { 522 setbits_be16(&gpio->par_feci2c, 0x00a0); 523 setbits_8(&gpio->par_fec1hl, 0xc0); 524 } 525 } else { 526 if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { 527 clrbits_be16(&gpio->par_feci2c, 0x0f00); 528 clrbits_8(&gpio->par_fec0hl, 0xc0); 529 } else { 530 clrbits_be16(&gpio->par_feci2c, 0x00a0); 531 clrbits_8(&gpio->par_fec1hl, 0xc0); 532 } 533 } 534 535 return 0; 536 } 537 #endif /* CONFIG_CMD_NET */ 538 #endif /* #if defined(CONFIG_M5275) */ 539 540 #if defined(CONFIG_M5282) 541 /* 542 * Breath some life into the CPU... 543 * 544 * Set up the memory map, 545 * initialize a bunch of registers, 546 * initialize the UPM's 547 */ 548 void cpu_init_f(void) 549 { 550 #ifndef CONFIG_WATCHDOG 551 /* disable watchdog if we aren't using it */ 552 MCFWTM_WCR = 0; 553 #endif 554 555 #ifndef CONFIG_MONITOR_IS_IN_RAM 556 /* Set speed /PLL */ 557 MCFCLOCK_SYNCR = 558 MCFCLOCK_SYNCR_MFD(CONFIG_SYS_MFD) | 559 MCFCLOCK_SYNCR_RFD(CONFIG_SYS_RFD); 560 while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ; 561 562 MCFGPIO_PBCDPAR = 0xc0; 563 564 /* Set up the GPIO ports */ 565 #ifdef CONFIG_SYS_PEPAR 566 MCFGPIO_PEPAR = CONFIG_SYS_PEPAR; 567 #endif 568 #ifdef CONFIG_SYS_PFPAR 569 MCFGPIO_PFPAR = CONFIG_SYS_PFPAR; 570 #endif 571 #ifdef CONFIG_SYS_PJPAR 572 MCFGPIO_PJPAR = CONFIG_SYS_PJPAR; 573 #endif 574 #ifdef CONFIG_SYS_PSDPAR 575 MCFGPIO_PSDPAR = CONFIG_SYS_PSDPAR; 576 #endif 577 #ifdef CONFIG_SYS_PASPAR 578 MCFGPIO_PASPAR = CONFIG_SYS_PASPAR; 579 #endif 580 #ifdef CONFIG_SYS_PEHLPAR 581 MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR; 582 #endif 583 #ifdef CONFIG_SYS_PQSPAR 584 MCFGPIO_PQSPAR = CONFIG_SYS_PQSPAR; 585 #endif 586 #ifdef CONFIG_SYS_PTCPAR 587 MCFGPIO_PTCPAR = CONFIG_SYS_PTCPAR; 588 #endif 589 #if defined(CONFIG_SYS_PORTTC) 590 MCFGPIO_PORTTC = CONFIG_SYS_PORTTC; 591 #endif 592 #if defined(CONFIG_SYS_DDRTC) 593 MCFGPIO_DDRTC = CONFIG_SYS_DDRTC; 594 #endif 595 #ifdef CONFIG_SYS_PTDPAR 596 MCFGPIO_PTDPAR = CONFIG_SYS_PTDPAR; 597 #endif 598 #ifdef CONFIG_SYS_PUAPAR 599 MCFGPIO_PUAPAR = CONFIG_SYS_PUAPAR; 600 #endif 601 602 #if defined(CONFIG_SYS_DDRD) 603 MCFGPIO_DDRD = CONFIG_SYS_DDRD; 604 #endif 605 #ifdef CONFIG_SYS_DDRUA 606 MCFGPIO_DDRUA = CONFIG_SYS_DDRUA; 607 #endif 608 609 /* FlexBus Chipselect */ 610 init_fbcs(); 611 612 #endif /* CONFIG_MONITOR_IS_IN_RAM */ 613 614 /* defer enabling cache until boot (see do_go) */ 615 /* icache_enable(); */ 616 } 617 618 /* 619 * initialize higher level parts of CPU like timers 620 */ 621 int cpu_init_r(void) 622 { 623 return (0); 624 } 625 626 void uart_port_conf(int port) 627 { 628 /* Setup Ports: */ 629 switch (port) { 630 case 0: 631 MCFGPIO_PUAPAR &= 0xFc; 632 MCFGPIO_PUAPAR |= 0x03; 633 break; 634 case 1: 635 MCFGPIO_PUAPAR &= 0xF3; 636 MCFGPIO_PUAPAR |= 0x0C; 637 break; 638 case 2: 639 MCFGPIO_PASPAR &= 0xFF0F; 640 MCFGPIO_PASPAR |= 0x00A0; 641 break; 642 } 643 } 644 645 #if defined(CONFIG_CMD_NET) 646 int fecpin_setclear(struct eth_device *dev, int setclear) 647 { 648 if (setclear) { 649 MCFGPIO_PASPAR |= 0x0F00; 650 MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR; 651 } else { 652 MCFGPIO_PASPAR &= 0xF0FF; 653 MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR; 654 } 655 return 0; 656 } 657 #endif /* CONFIG_CMD_NET */ 658 #endif 659 660 #if defined(CONFIG_M5249) 661 /* 662 * Breath some life into the CPU... 663 * 664 * Set up the memory map, 665 * initialize a bunch of registers, 666 * initialize the UPM's 667 */ 668 void cpu_init_f(void) 669 { 670 /* 671 * NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins 672 * (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins 673 * which is their primary function. 674 * ~Jeremy 675 */ 676 mbar2_writeLong(MCFSIM_GPIO_FUNC, CONFIG_SYS_GPIO_FUNC); 677 mbar2_writeLong(MCFSIM_GPIO1_FUNC, CONFIG_SYS_GPIO1_FUNC); 678 mbar2_writeLong(MCFSIM_GPIO_EN, CONFIG_SYS_GPIO_EN); 679 mbar2_writeLong(MCFSIM_GPIO1_EN, CONFIG_SYS_GPIO1_EN); 680 mbar2_writeLong(MCFSIM_GPIO_OUT, CONFIG_SYS_GPIO_OUT); 681 mbar2_writeLong(MCFSIM_GPIO1_OUT, CONFIG_SYS_GPIO1_OUT); 682 683 /* 684 * dBug Compliance: 685 * You can verify these values by using dBug's 'ird' 686 * (Internal Register Display) command 687 * ~Jeremy 688 * 689 */ 690 mbar_writeByte(MCFSIM_MPARK, 0x30); /* 5249 Internal Core takes priority over DMA */ 691 mbar_writeByte(MCFSIM_SYPCR, 0x00); 692 mbar_writeByte(MCFSIM_SWIVR, 0x0f); 693 mbar_writeByte(MCFSIM_SWSR, 0x00); 694 mbar_writeLong(MCFSIM_IMR, 0xfffffbff); 695 mbar_writeByte(MCFSIM_SWDICR, 0x00); 696 mbar_writeByte(MCFSIM_TIMER1ICR, 0x00); 697 mbar_writeByte(MCFSIM_TIMER2ICR, 0x88); 698 mbar_writeByte(MCFSIM_I2CICR, 0x00); 699 mbar_writeByte(MCFSIM_UART1ICR, 0x00); 700 mbar_writeByte(MCFSIM_UART2ICR, 0x00); 701 mbar_writeByte(MCFSIM_ICR6, 0x00); 702 mbar_writeByte(MCFSIM_ICR7, 0x00); 703 mbar_writeByte(MCFSIM_ICR8, 0x00); 704 mbar_writeByte(MCFSIM_ICR9, 0x00); 705 mbar_writeByte(MCFSIM_QSPIICR, 0x00); 706 707 mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080); 708 mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */ 709 mbar2_writeByte(MCFSIM_SPURVEC, 0x00); 710 mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */ 711 712 /* Setup interrupt priorities for gpio7 */ 713 /* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */ 714 715 /* IDE Config registers */ 716 mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); 717 mbar2_writeLong(MCFSIM_IDECONFIG2, 0x00000000); 718 719 /* FlexBus Chipselect */ 720 init_fbcs(); 721 722 /* enable instruction cache now */ 723 icache_enable(); 724 } 725 726 /* 727 * initialize higher level parts of CPU like timers 728 */ 729 int cpu_init_r(void) 730 { 731 return (0); 732 } 733 734 void uart_port_conf(int port) 735 { 736 } 737 #endif /* #if defined(CONFIG_M5249) */ 738