1 /* 2 * (C) Copyright 2003 3 * Josef Baumgartner <josef.baumgartner@telex.de> 4 * 5 * MCF5282 additionals 6 * (C) Copyright 2005 7 * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de> 8 * (c) Copyright 2010 9 * Arcturus Networks Inc. <www.arcturusnetworks.com> 10 * 11 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. 12 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 13 * Hayden Fraser (Hayden.Fraser@freescale.com) 14 * 15 * MCF5275 additions 16 * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com) 17 * 18 * SPDX-License-Identifier: GPL-2.0+ 19 */ 20 21 #include <common.h> 22 #include <watchdog.h> 23 #include <asm/immap.h> 24 #include <asm/io.h> 25 26 #if defined(CONFIG_CMD_NET) 27 #include <config.h> 28 #include <net.h> 29 #include <asm/fec.h> 30 #endif 31 32 #ifndef CONFIG_M5272 33 /* Only 5272 Flexbus chipselect is different from the rest */ 34 void init_fbcs(void) 35 { 36 fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS); 37 38 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ 39 && defined(CONFIG_SYS_CS0_CTRL)) 40 out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); 41 out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); 42 out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); 43 #else 44 #warning "Chip Select 0 are not initialized/used" 45 #endif 46 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ 47 && defined(CONFIG_SYS_CS1_CTRL)) 48 out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); 49 out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); 50 out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); 51 #endif 52 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ 53 && defined(CONFIG_SYS_CS2_CTRL)) 54 out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); 55 out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); 56 out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); 57 #endif 58 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ 59 && defined(CONFIG_SYS_CS3_CTRL)) 60 out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); 61 out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); 62 out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); 63 #endif 64 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ 65 && defined(CONFIG_SYS_CS4_CTRL)) 66 out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE); 67 out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL); 68 out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK); 69 #endif 70 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \ 71 && defined(CONFIG_SYS_CS5_CTRL)) 72 out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE); 73 out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL); 74 out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK); 75 #endif 76 #if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) \ 77 && defined(CONFIG_SYS_CS6_CTRL)) 78 out_be32(&fbcs->csar6, CONFIG_SYS_CS6_BASE); 79 out_be32(&fbcs->cscr6, CONFIG_SYS_CS6_CTRL); 80 out_be32(&fbcs->csmr6, CONFIG_SYS_CS6_MASK); 81 #endif 82 #if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) \ 83 && defined(CONFIG_SYS_CS7_CTRL)) 84 out_be32(&fbcs->csar7, CONFIG_SYS_CS7_BASE); 85 out_be32(&fbcs->cscr7, CONFIG_SYS_CS7_CTRL); 86 out_be32(&fbcs->csmr7, CONFIG_SYS_CS7_MASK); 87 #endif 88 } 89 #endif 90 91 #if defined(CONFIG_M5208) 92 void cpu_init_f(void) 93 { 94 scm1_t *scm1 = (scm1_t *) MMAP_SCM1; 95 96 #ifndef CONFIG_WATCHDOG 97 wdog_t *wdg = (wdog_t *) MMAP_WDOG; 98 99 /* Disable the watchdog if we aren't using it */ 100 out_be16(&wdg->cr, 0); 101 #endif 102 103 out_be32(&scm1->mpr, 0x77777777); 104 out_be32(&scm1->pacra, 0); 105 out_be32(&scm1->pacrb, 0); 106 out_be32(&scm1->pacrc, 0); 107 out_be32(&scm1->pacrd, 0); 108 out_be32(&scm1->pacre, 0); 109 out_be32(&scm1->pacrf, 0); 110 111 /* FlexBus Chipselect */ 112 init_fbcs(); 113 114 icache_enable(); 115 } 116 117 /* initialize higher level parts of CPU like timers */ 118 int cpu_init_r(void) 119 { 120 return (0); 121 } 122 123 void uart_port_conf(int port) 124 { 125 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 126 127 /* Setup Ports: */ 128 switch (port) { 129 case 0: 130 clrbits_be16(&gpio->par_uart, ~GPIO_PAR_UART0_UNMASK); 131 setbits_be16(&gpio->par_uart, GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD); 132 break; 133 case 1: 134 clrbits_be16(&gpio->par_uart, ~GPIO_PAR_UART0_UNMASK); 135 setbits_be16(&gpio->par_uart, GPIO_PAR_UART_U1TXD | GPIO_PAR_UART_U1RXD); 136 break; 137 case 2: 138 #ifdef CONFIG_SYS_UART2_PRI_GPIO 139 clrbits_8(&gpio->par_timer, 140 ~(GPIO_PAR_TMR_TIN0_UNMASK | GPIO_PAR_TMR_TIN1_UNMASK)); 141 setbits_8(&gpio->par_timer, 142 GPIO_PAR_TMR_TIN0_U2TXD | GPIO_PAR_TMR_TIN1_U2RXD); 143 #endif 144 #ifdef CONFIG_SYS_UART2_ALT1_GPIO 145 clrbits_8(&gpio->par_feci2c, 146 ~(GPIO_PAR_FECI2C_MDC_UNMASK | GPIO_PAR_FECI2C_MDIO_UNMASK)); 147 setbits_8(&gpio->par_feci2c, 148 GPIO_PAR_FECI2C_MDC_U2TXD | GPIO_PAR_FECI2C_MDIO_U2RXD); 149 #endif 150 #ifdef CONFIG_SYS_UART2_ALT1_GPIO 151 clrbits_8(&gpio->par_feci2c, 152 ~(GPIO_PAR_FECI2C_SDA_UNMASK | GPIO_PAR_FECI2C_SCL_UNMASK)); 153 setbits_8(&gpio->par_feci2c, 154 GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD); 155 #endif 156 break; 157 } 158 } 159 160 #if defined(CONFIG_CMD_NET) 161 int fecpin_setclear(struct eth_device *dev, int setclear) 162 { 163 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 164 165 if (setclear) { 166 setbits_8(&gpio->par_fec, 167 GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC); 168 setbits_8(&gpio->par_feci2c, 169 GPIO_PAR_FECI2C_MDC_MDC | GPIO_PAR_FECI2C_MDIO_MDIO); 170 } else { 171 clrbits_8(&gpio->par_fec, 172 ~(GPIO_PAR_FEC_7W_UNMASK & GPIO_PAR_FEC_MII_UNMASK)); 173 clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII_UNMASK); 174 } 175 return 0; 176 } 177 #endif /* CONFIG_CMD_NET */ 178 #endif /* CONFIG_M5208 */ 179 180 #if defined(CONFIG_M5253) 181 /* 182 * Breath some life into the CPU... 183 * 184 * Set up the memory map, 185 * initialize a bunch of registers, 186 * initialize the UPM's 187 */ 188 void cpu_init_f(void) 189 { 190 mbar_writeByte(MCFSIM_MPARK, 0x40); /* 5249 Internal Core takes priority over DMA */ 191 mbar_writeByte(MCFSIM_SYPCR, 0x00); 192 mbar_writeByte(MCFSIM_SWIVR, 0x0f); 193 mbar_writeByte(MCFSIM_SWSR, 0x00); 194 mbar_writeByte(MCFSIM_SWDICR, 0x00); 195 mbar_writeByte(MCFSIM_TIMER1ICR, 0x00); 196 mbar_writeByte(MCFSIM_TIMER2ICR, 0x88); 197 mbar_writeByte(MCFSIM_I2CICR, 0x00); 198 mbar_writeByte(MCFSIM_UART1ICR, 0x00); 199 mbar_writeByte(MCFSIM_UART2ICR, 0x00); 200 mbar_writeByte(MCFSIM_ICR6, 0x00); 201 mbar_writeByte(MCFSIM_ICR7, 0x00); 202 mbar_writeByte(MCFSIM_ICR8, 0x00); 203 mbar_writeByte(MCFSIM_ICR9, 0x00); 204 mbar_writeByte(MCFSIM_QSPIICR, 0x00); 205 206 mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080); 207 mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */ 208 mbar2_writeByte(MCFSIM_SPURVEC, 0x00); 209 210 /*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */ 211 212 /* FlexBus Chipselect */ 213 init_fbcs(); 214 215 #ifdef CONFIG_SYS_I2C_FSL 216 CONFIG_SYS_I2C_PINMUX_REG = 217 CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR; 218 CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET; 219 #ifdef CONFIG_SYS_I2C2_OFFSET 220 CONFIG_SYS_I2C2_PINMUX_REG &= CONFIG_SYS_I2C2_PINMUX_CLR; 221 CONFIG_SYS_I2C2_PINMUX_REG |= CONFIG_SYS_I2C2_PINMUX_SET; 222 #endif 223 #endif 224 225 /* enable instruction cache now */ 226 icache_enable(); 227 } 228 229 /*initialize higher level parts of CPU like timers */ 230 int cpu_init_r(void) 231 { 232 return (0); 233 } 234 235 void uart_port_conf(int port) 236 { 237 u32 *par = (u32 *) MMAP_PAR; 238 239 /* Setup Ports: */ 240 switch (port) { 241 case 1: 242 clrbits_be32(par, 0x00180000); 243 setbits_be32(par, 0x00180000); 244 break; 245 case 2: 246 clrbits_be32(par, 0x00000003); 247 clrbits_be32(par, 0xFFFFFFFC); 248 break; 249 } 250 } 251 #endif /* #if defined(CONFIG_M5253) */ 252 253 #if defined(CONFIG_M5271) 254 void cpu_init_f(void) 255 { 256 #ifndef CONFIG_WATCHDOG 257 /* Disable the watchdog if we aren't using it */ 258 mbar_writeShort(MCF_WTM_WCR, 0); 259 #endif 260 261 /* FlexBus Chipselect */ 262 init_fbcs(); 263 264 #ifdef CONFIG_SYS_MCF_SYNCR 265 /* Set clockspeed according to board header file */ 266 mbar_writeLong(MCF_FMPLL_SYNCR, CONFIG_SYS_MCF_SYNCR); 267 #else 268 /* Set clockspeed to 100MHz */ 269 mbar_writeLong(MCF_FMPLL_SYNCR, 270 MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0)); 271 #endif 272 while (!(mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK)) ; 273 } 274 275 /* 276 * initialize higher level parts of CPU like timers 277 */ 278 int cpu_init_r(void) 279 { 280 return (0); 281 } 282 283 void uart_port_conf(int port) 284 { 285 u16 temp; 286 287 /* Setup Ports: */ 288 switch (port) { 289 case 0: 290 temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xFFF3; 291 temp |= (MCF_GPIO_PAR_UART_U0TXD | MCF_GPIO_PAR_UART_U0RXD); 292 mbar_writeShort(MCF_GPIO_PAR_UART, temp); 293 break; 294 case 1: 295 temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xF0FF; 296 temp |= (MCF_GPIO_PAR_UART_U1RXD_UART1 | MCF_GPIO_PAR_UART_U1TXD_UART1); 297 mbar_writeShort(MCF_GPIO_PAR_UART, temp); 298 break; 299 case 2: 300 temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xCFFF; 301 temp |= (0x3000); 302 mbar_writeShort(MCF_GPIO_PAR_UART, temp); 303 break; 304 } 305 } 306 307 #if defined(CONFIG_CMD_NET) 308 int fecpin_setclear(struct eth_device *dev, int setclear) 309 { 310 if (setclear) { 311 /* Enable Ethernet pins */ 312 mbar_writeByte(MCF_GPIO_PAR_FECI2C, 313 (mbar_readByte(MCF_GPIO_PAR_FECI2C) | 0xF0)); 314 } else { 315 } 316 317 return 0; 318 } 319 #endif /* CONFIG_CMD_NET */ 320 321 #if defined(CONFIG_CF_QSPI) 322 323 /* Configure PIOs for SIN, SOUT, and SCK */ 324 void cfspi_port_conf(void) 325 { 326 mbar_writeByte(MCF_GPIO_PAR_QSPI, 327 MCF_GPIO_PAR_QSPI_SIN_SIN | 328 MCF_GPIO_PAR_QSPI_SOUT_SOUT | 329 MCF_GPIO_PAR_QSPI_SCK_SCK); 330 } 331 #endif /* CONFIG_CF_QSPI */ 332 333 #endif /* CONFIG_M5271 */ 334 335 #if defined(CONFIG_M5272) 336 /* 337 * Breath some life into the CPU... 338 * 339 * Set up the memory map, 340 * initialize a bunch of registers, 341 * initialize the UPM's 342 */ 343 void cpu_init_f(void) 344 { 345 /* if we come from RAM we assume the CPU is 346 * already initialized. 347 */ 348 #ifndef CONFIG_MONITOR_IS_IN_RAM 349 sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR); 350 gpio_t *gpio = (gpio_t *) (MMAP_GPIO); 351 csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS); 352 353 out_be16(&sysctrl->sc_scr, CONFIG_SYS_SCR); 354 out_be16(&sysctrl->sc_spr, CONFIG_SYS_SPR); 355 356 /* Setup Ports: */ 357 out_be32(&gpio->gpio_pacnt, CONFIG_SYS_PACNT); 358 out_be16(&gpio->gpio_paddr, CONFIG_SYS_PADDR); 359 out_be16(&gpio->gpio_padat, CONFIG_SYS_PADAT); 360 out_be32(&gpio->gpio_pbcnt, CONFIG_SYS_PBCNT); 361 out_be16(&gpio->gpio_pbddr, CONFIG_SYS_PBDDR); 362 out_be16(&gpio->gpio_pbdat, CONFIG_SYS_PBDAT); 363 out_be32(&gpio->gpio_pdcnt, CONFIG_SYS_PDCNT); 364 365 /* Memory Controller: */ 366 out_be32(&csctrl->cs_br0, CONFIG_SYS_BR0_PRELIM); 367 out_be32(&csctrl->cs_or0, CONFIG_SYS_OR0_PRELIM); 368 369 #if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM)) 370 out_be32(&csctrl->cs_br1, CONFIG_SYS_BR1_PRELIM); 371 out_be32(&csctrl->cs_or1, CONFIG_SYS_OR1_PRELIM); 372 #endif 373 374 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) 375 out_be32(&csctrl->cs_br2, CONFIG_SYS_BR2_PRELIM); 376 out_be32(&csctrl->cs_or2, CONFIG_SYS_OR2_PRELIM); 377 #endif 378 379 #if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM) 380 out_be32(&csctrl->cs_br3, CONFIG_SYS_BR3_PRELIM); 381 out_be32(&csctrl->cs_or3, CONFIG_SYS_OR3_PRELIM); 382 #endif 383 384 #if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM) 385 out_be32(&csctrl->cs_br4, CONFIG_SYS_BR4_PRELIM); 386 out_be32(&csctrl->cs_or4, CONFIG_SYS_OR4_PRELIM); 387 #endif 388 389 #if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM) 390 out_be32(&csctrl->cs_br5, CONFIG_SYS_BR5_PRELIM); 391 out_be32(&csctrl->cs_or5, CONFIG_SYS_OR5_PRELIM); 392 #endif 393 394 #if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM) 395 out_be32(&csctrl->cs_br6, CONFIG_SYS_BR6_PRELIM); 396 out_be32(&csctrl->cs_or6, CONFIG_SYS_OR6_PRELIM); 397 #endif 398 399 #if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM) 400 out_be32(&csctrl->cs_br7, CONFIG_SYS_BR7_PRELIM); 401 out_be32(&csctrl->cs_or7, CONFIG_SYS_OR7_PRELIM); 402 #endif 403 404 #endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */ 405 406 /* enable instruction cache now */ 407 icache_enable(); 408 409 } 410 411 /* 412 * initialize higher level parts of CPU like timers 413 */ 414 int cpu_init_r(void) 415 { 416 return (0); 417 } 418 419 void uart_port_conf(int port) 420 { 421 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 422 423 /* Setup Ports: */ 424 switch (port) { 425 case 0: 426 clrbits_be32(&gpio->gpio_pbcnt, 427 GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK); 428 setbits_be32(&gpio->gpio_pbcnt, 429 GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD); 430 break; 431 case 1: 432 clrbits_be32(&gpio->gpio_pdcnt, 433 GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK); 434 setbits_be32(&gpio->gpio_pdcnt, 435 GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD); 436 break; 437 } 438 } 439 440 #if defined(CONFIG_CMD_NET) 441 int fecpin_setclear(struct eth_device *dev, int setclear) 442 { 443 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 444 445 if (setclear) { 446 setbits_be32(&gpio->gpio_pbcnt, 447 GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER | 448 GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 | 449 GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 | 450 GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3); 451 } else { 452 } 453 return 0; 454 } 455 #endif /* CONFIG_CMD_NET */ 456 #endif /* #if defined(CONFIG_M5272) */ 457 458 #if defined(CONFIG_M5275) 459 460 /* 461 * Breathe some life into the CPU... 462 * 463 * Set up the memory map, 464 * initialize a bunch of registers, 465 * initialize the UPM's 466 */ 467 void cpu_init_f(void) 468 { 469 /* 470 * if we come from RAM we assume the CPU is 471 * already initialized. 472 */ 473 474 #ifndef CONFIG_MONITOR_IS_IN_RAM 475 wdog_t *wdog_reg = (wdog_t *) (MMAP_WDOG); 476 gpio_t *gpio_reg = (gpio_t *) (MMAP_GPIO); 477 478 /* Kill watchdog so we can initialize the PLL */ 479 out_be16(&wdog_reg->wcr, 0); 480 481 /* FlexBus Chipselect */ 482 init_fbcs(); 483 #endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */ 484 485 #ifdef CONFIG_SYS_I2C_FSL 486 CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR; 487 CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET; 488 #endif 489 490 /* enable instruction cache now */ 491 icache_enable(); 492 } 493 494 /* 495 * initialize higher level parts of CPU like timers 496 */ 497 int cpu_init_r(void) 498 { 499 return (0); 500 } 501 502 void uart_port_conf(int port) 503 { 504 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 505 506 /* Setup Ports: */ 507 switch (port) { 508 case 0: 509 clrbits_be16(&gpio->par_uart, UART0_ENABLE_MASK); 510 setbits_be16(&gpio->par_uart, UART0_ENABLE_MASK); 511 break; 512 case 1: 513 clrbits_be16(&gpio->par_uart, UART1_ENABLE_MASK); 514 setbits_be16(&gpio->par_uart, UART1_ENABLE_MASK); 515 break; 516 case 2: 517 clrbits_be16(&gpio->par_uart, UART2_ENABLE_MASK); 518 setbits_be16(&gpio->par_uart, UART2_ENABLE_MASK); 519 break; 520 } 521 } 522 523 #if defined(CONFIG_CMD_NET) 524 int fecpin_setclear(struct eth_device *dev, int setclear) 525 { 526 struct fec_info_s *info = (struct fec_info_s *) dev->priv; 527 gpio_t *gpio = (gpio_t *)MMAP_GPIO; 528 529 if (setclear) { 530 /* Enable Ethernet pins */ 531 if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { 532 setbits_be16(&gpio->par_feci2c, 0x0f00); 533 setbits_8(&gpio->par_fec0hl, 0xc0); 534 } else { 535 setbits_be16(&gpio->par_feci2c, 0x00a0); 536 setbits_8(&gpio->par_fec1hl, 0xc0); 537 } 538 } else { 539 if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { 540 clrbits_be16(&gpio->par_feci2c, 0x0f00); 541 clrbits_8(&gpio->par_fec0hl, 0xc0); 542 } else { 543 clrbits_be16(&gpio->par_feci2c, 0x00a0); 544 clrbits_8(&gpio->par_fec1hl, 0xc0); 545 } 546 } 547 548 return 0; 549 } 550 #endif /* CONFIG_CMD_NET */ 551 #endif /* #if defined(CONFIG_M5275) */ 552 553 #if defined(CONFIG_M5282) 554 /* 555 * Breath some life into the CPU... 556 * 557 * Set up the memory map, 558 * initialize a bunch of registers, 559 * initialize the UPM's 560 */ 561 void cpu_init_f(void) 562 { 563 #ifndef CONFIG_WATCHDOG 564 /* disable watchdog if we aren't using it */ 565 MCFWTM_WCR = 0; 566 #endif 567 568 #ifndef CONFIG_MONITOR_IS_IN_RAM 569 /* Set speed /PLL */ 570 MCFCLOCK_SYNCR = 571 MCFCLOCK_SYNCR_MFD(CONFIG_SYS_MFD) | 572 MCFCLOCK_SYNCR_RFD(CONFIG_SYS_RFD); 573 while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ; 574 575 MCFGPIO_PBCDPAR = 0xc0; 576 577 /* Set up the GPIO ports */ 578 #ifdef CONFIG_SYS_PEPAR 579 MCFGPIO_PEPAR = CONFIG_SYS_PEPAR; 580 #endif 581 #ifdef CONFIG_SYS_PFPAR 582 MCFGPIO_PFPAR = CONFIG_SYS_PFPAR; 583 #endif 584 #ifdef CONFIG_SYS_PJPAR 585 MCFGPIO_PJPAR = CONFIG_SYS_PJPAR; 586 #endif 587 #ifdef CONFIG_SYS_PSDPAR 588 MCFGPIO_PSDPAR = CONFIG_SYS_PSDPAR; 589 #endif 590 #ifdef CONFIG_SYS_PASPAR 591 MCFGPIO_PASPAR = CONFIG_SYS_PASPAR; 592 #endif 593 #ifdef CONFIG_SYS_PEHLPAR 594 MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR; 595 #endif 596 #ifdef CONFIG_SYS_PQSPAR 597 MCFGPIO_PQSPAR = CONFIG_SYS_PQSPAR; 598 #endif 599 #ifdef CONFIG_SYS_PTCPAR 600 MCFGPIO_PTCPAR = CONFIG_SYS_PTCPAR; 601 #endif 602 #if defined(CONFIG_SYS_PORTTC) 603 MCFGPIO_PORTTC = CONFIG_SYS_PORTTC; 604 #endif 605 #if defined(CONFIG_SYS_DDRTC) 606 MCFGPIO_DDRTC = CONFIG_SYS_DDRTC; 607 #endif 608 #ifdef CONFIG_SYS_PTDPAR 609 MCFGPIO_PTDPAR = CONFIG_SYS_PTDPAR; 610 #endif 611 #ifdef CONFIG_SYS_PUAPAR 612 MCFGPIO_PUAPAR = CONFIG_SYS_PUAPAR; 613 #endif 614 615 #if defined(CONFIG_SYS_DDRD) 616 MCFGPIO_DDRD = CONFIG_SYS_DDRD; 617 #endif 618 #ifdef CONFIG_SYS_DDRUA 619 MCFGPIO_DDRUA = CONFIG_SYS_DDRUA; 620 #endif 621 622 /* FlexBus Chipselect */ 623 init_fbcs(); 624 625 #endif /* CONFIG_MONITOR_IS_IN_RAM */ 626 627 /* defer enabling cache until boot (see do_go) */ 628 /* icache_enable(); */ 629 } 630 631 /* 632 * initialize higher level parts of CPU like timers 633 */ 634 int cpu_init_r(void) 635 { 636 return (0); 637 } 638 639 void uart_port_conf(int port) 640 { 641 /* Setup Ports: */ 642 switch (port) { 643 case 0: 644 MCFGPIO_PUAPAR &= 0xFc; 645 MCFGPIO_PUAPAR |= 0x03; 646 break; 647 case 1: 648 MCFGPIO_PUAPAR &= 0xF3; 649 MCFGPIO_PUAPAR |= 0x0C; 650 break; 651 case 2: 652 MCFGPIO_PASPAR &= 0xFF0F; 653 MCFGPIO_PASPAR |= 0x00A0; 654 break; 655 } 656 } 657 658 #if defined(CONFIG_CMD_NET) 659 int fecpin_setclear(struct eth_device *dev, int setclear) 660 { 661 if (setclear) { 662 MCFGPIO_PASPAR |= 0x0F00; 663 MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR; 664 } else { 665 MCFGPIO_PASPAR &= 0xF0FF; 666 MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR; 667 } 668 return 0; 669 } 670 #endif /* CONFIG_CMD_NET */ 671 #endif 672 673 #if defined(CONFIG_M5249) 674 /* 675 * Breath some life into the CPU... 676 * 677 * Set up the memory map, 678 * initialize a bunch of registers, 679 * initialize the UPM's 680 */ 681 void cpu_init_f(void) 682 { 683 /* 684 * NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins 685 * (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins 686 * which is their primary function. 687 * ~Jeremy 688 */ 689 mbar2_writeLong(MCFSIM_GPIO_FUNC, CONFIG_SYS_GPIO_FUNC); 690 mbar2_writeLong(MCFSIM_GPIO1_FUNC, CONFIG_SYS_GPIO1_FUNC); 691 mbar2_writeLong(MCFSIM_GPIO_EN, CONFIG_SYS_GPIO_EN); 692 mbar2_writeLong(MCFSIM_GPIO1_EN, CONFIG_SYS_GPIO1_EN); 693 mbar2_writeLong(MCFSIM_GPIO_OUT, CONFIG_SYS_GPIO_OUT); 694 mbar2_writeLong(MCFSIM_GPIO1_OUT, CONFIG_SYS_GPIO1_OUT); 695 696 /* 697 * dBug Compliance: 698 * You can verify these values by using dBug's 'ird' 699 * (Internal Register Display) command 700 * ~Jeremy 701 * 702 */ 703 mbar_writeByte(MCFSIM_MPARK, 0x30); /* 5249 Internal Core takes priority over DMA */ 704 mbar_writeByte(MCFSIM_SYPCR, 0x00); 705 mbar_writeByte(MCFSIM_SWIVR, 0x0f); 706 mbar_writeByte(MCFSIM_SWSR, 0x00); 707 mbar_writeLong(MCFSIM_IMR, 0xfffffbff); 708 mbar_writeByte(MCFSIM_SWDICR, 0x00); 709 mbar_writeByte(MCFSIM_TIMER1ICR, 0x00); 710 mbar_writeByte(MCFSIM_TIMER2ICR, 0x88); 711 mbar_writeByte(MCFSIM_I2CICR, 0x00); 712 mbar_writeByte(MCFSIM_UART1ICR, 0x00); 713 mbar_writeByte(MCFSIM_UART2ICR, 0x00); 714 mbar_writeByte(MCFSIM_ICR6, 0x00); 715 mbar_writeByte(MCFSIM_ICR7, 0x00); 716 mbar_writeByte(MCFSIM_ICR8, 0x00); 717 mbar_writeByte(MCFSIM_ICR9, 0x00); 718 mbar_writeByte(MCFSIM_QSPIICR, 0x00); 719 720 mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080); 721 mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */ 722 mbar2_writeByte(MCFSIM_SPURVEC, 0x00); 723 mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */ 724 725 /* Setup interrupt priorities for gpio7 */ 726 /* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */ 727 728 /* IDE Config registers */ 729 mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); 730 mbar2_writeLong(MCFSIM_IDECONFIG2, 0x00000000); 731 732 /* FlexBus Chipselect */ 733 init_fbcs(); 734 735 /* enable instruction cache now */ 736 icache_enable(); 737 } 738 739 /* 740 * initialize higher level parts of CPU like timers 741 */ 742 int cpu_init_r(void) 743 { 744 return (0); 745 } 746 747 void uart_port_conf(int port) 748 { 749 } 750 #endif /* #if defined(CONFIG_M5249) */ 751