1 /* 2 * (C) Copyright 2003 3 * Josef Baumgartner <josef.baumgartner@telex.de> 4 * 5 * MCF5282 additionals 6 * (C) Copyright 2005 7 * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de> 8 * 9 * MCF5275 additions 10 * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com) 11 * 12 * See file CREDITS for list of people who contributed to this 13 * project. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of 18 * the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 28 * MA 02111-1307 USA 29 */ 30 31 #include <common.h> 32 #include <watchdog.h> 33 #include <command.h> 34 #include <asm/immap.h> 35 #include <netdev.h> 36 #include "cpu.h" 37 38 DECLARE_GLOBAL_DATA_PTR; 39 40 #ifdef CONFIG_M5208 41 int do_reset(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char * const argv[]) 42 { 43 volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM); 44 45 udelay(1000); 46 47 rcm->rcr = RCM_RCR_SOFTRST; 48 49 /* we don't return! */ 50 return 0; 51 }; 52 53 int checkcpu(void) 54 { 55 char buf1[32], buf2[32]; 56 57 printf("CPU: Freescale Coldfire MCF5208\n" 58 " CPU CLK %s MHz BUS CLK %s MHz\n", 59 strmhz(buf1, gd->cpu_clk), 60 strmhz(buf2, gd->bus_clk)); 61 return 0; 62 }; 63 64 #if defined(CONFIG_WATCHDOG) 65 /* Called by macro WATCHDOG_RESET */ 66 void watchdog_reset(void) 67 { 68 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); 69 wdt->sr = 0x5555; 70 wdt->sr = 0xAAAA; 71 } 72 73 int watchdog_disable(void) 74 { 75 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); 76 77 wdt->sr = 0x5555; /* reset watchdog counteDECLARE_GLOBAL_DATA_PTR; 78 r */ 79 wdt->sr = 0xAAAA; 80 wdt->cr = 0; /* disable watchdog timer */ 81 82 puts("WATCHDOG:disabled\n"); 83 return (0); 84 } 85 86 int watchdog_init(void) 87 { 88 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); 89 90 wdt->cr = 0; /* disable watchdog */ 91 92 /* set timeout and enable watchdog */ 93 wdt->mr = 94 ((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1; 95 wdt->sr = 0x5555; /* reset watchdog counter */ 96 wdt->sr = 0xAAAA; 97 98 puts("WATCHDOG:enabled\n"); 99 return (0); 100 } 101 #endif /* #ifdef CONFIG_WATCHDOG */ 102 #endif /* #ifdef CONFIG_M5208 */ 103 104 #ifdef CONFIG_M5271 105 /* 106 * Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to 107 * determine which one we are running on, based on the Chip Identification 108 * Register (CIR). 109 */ 110 int checkcpu(void) 111 { 112 char buf[32]; 113 unsigned short cir; /* Chip Identification Register */ 114 unsigned short pin; /* Part identification number */ 115 unsigned char prn; /* Part revision number */ 116 char *cpu_model; 117 118 cir = mbar_readShort(MCF_CCM_CIR); 119 pin = cir >> MCF_CCM_CIR_PIN_LEN; 120 prn = cir & MCF_CCM_CIR_PRN_MASK; 121 122 switch (pin) { 123 case MCF_CCM_CIR_PIN_MCF5270: 124 cpu_model = "5270"; 125 break; 126 case MCF_CCM_CIR_PIN_MCF5271: 127 cpu_model = "5271"; 128 break; 129 default: 130 cpu_model = NULL; 131 break; 132 } 133 134 if (cpu_model) 135 printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n", 136 cpu_model, prn, strmhz(buf, CONFIG_SYS_CLK)); 137 else 138 printf("CPU: Unknown - Freescale ColdFire MCF5271 family" 139 " (PIN: 0x%x) rev. %hu, at %s MHz\n", 140 pin, prn, strmhz(buf, CONFIG_SYS_CLK)); 141 142 return 0; 143 } 144 145 int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[]) 146 { 147 /* Call the board specific reset actions first. */ 148 if(board_reset) { 149 board_reset(); 150 } 151 152 mbar_writeByte(MCF_RCM_RCR, 153 MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT); 154 return 0; 155 }; 156 157 #if defined(CONFIG_WATCHDOG) 158 void watchdog_reset(void) 159 { 160 mbar_writeShort(MCF_WTM_WSR, 0x5555); 161 mbar_writeShort(MCF_WTM_WSR, 0xAAAA); 162 } 163 164 int watchdog_disable(void) 165 { 166 mbar_writeShort(MCF_WTM_WCR, 0); 167 return (0); 168 } 169 170 int watchdog_init(void) 171 { 172 mbar_writeShort(MCF_WTM_WCR, MCF_WTM_WCR_EN); 173 return (0); 174 } 175 #endif /* #ifdef CONFIG_WATCHDOG */ 176 177 #endif 178 179 #ifdef CONFIG_M5272 180 int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[]) 181 { 182 volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG); 183 184 wdp->wdog_wrrr = 0; 185 udelay(1000); 186 187 /* enable watchdog, set timeout to 0 and wait */ 188 wdp->wdog_wrrr = 1; 189 while (1) ; 190 191 /* we don't return! */ 192 return 0; 193 }; 194 195 int checkcpu(void) 196 { 197 volatile sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG); 198 uchar msk; 199 char *suf; 200 201 puts("CPU: "); 202 msk = (sysctrl->sc_dir > 28) & 0xf; 203 switch (msk) { 204 case 0x2: 205 suf = "1K75N"; 206 break; 207 case 0x4: 208 suf = "3K75N"; 209 break; 210 default: 211 suf = NULL; 212 printf("Freescale MCF5272 (Mask:%01x)\n", msk); 213 break; 214 } 215 216 if (suf) 217 printf("Freescale MCF5272 %s\n", suf); 218 return 0; 219 }; 220 221 #if defined(CONFIG_WATCHDOG) 222 /* Called by macro WATCHDOG_RESET */ 223 void watchdog_reset(void) 224 { 225 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); 226 wdt->wdog_wcr = 0; 227 } 228 229 int watchdog_disable(void) 230 { 231 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); 232 233 wdt->wdog_wcr = 0; /* reset watchdog counter */ 234 wdt->wdog_wirr = 0; /* disable watchdog interrupt */ 235 wdt->wdog_wrrr = 0; /* disable watchdog timer */ 236 237 puts("WATCHDOG:disabled\n"); 238 return (0); 239 } 240 241 int watchdog_init(void) 242 { 243 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); 244 245 wdt->wdog_wirr = 0; /* disable watchdog interrupt */ 246 247 /* set timeout and enable watchdog */ 248 wdt->wdog_wrrr = 249 ((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1; 250 wdt->wdog_wcr = 0; /* reset watchdog counter */ 251 252 puts("WATCHDOG:enabled\n"); 253 return (0); 254 } 255 #endif /* #ifdef CONFIG_WATCHDOG */ 256 257 #endif /* #ifdef CONFIG_M5272 */ 258 259 #ifdef CONFIG_M5275 260 int do_reset(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char * const argv[]) 261 { 262 volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM); 263 264 udelay(1000); 265 266 rcm->rcr = RCM_RCR_SOFTRST; 267 268 /* we don't return! */ 269 return 0; 270 }; 271 272 int checkcpu(void) 273 { 274 char buf[32]; 275 276 printf("CPU: Freescale Coldfire MCF5275 at %s MHz\n", 277 strmhz(buf, CONFIG_SYS_CLK)); 278 return 0; 279 }; 280 281 282 #if defined(CONFIG_WATCHDOG) 283 /* Called by macro WATCHDOG_RESET */ 284 void watchdog_reset(void) 285 { 286 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); 287 wdt->wsr = 0x5555; 288 wdt->wsr = 0xAAAA; 289 } 290 291 int watchdog_disable(void) 292 { 293 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); 294 295 wdt->wsr = 0x5555; /* reset watchdog counter */ 296 wdt->wsr = 0xAAAA; 297 wdt->wcr = 0; /* disable watchdog timer */ 298 299 puts("WATCHDOG:disabled\n"); 300 return (0); 301 } 302 303 int watchdog_init(void) 304 { 305 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); 306 307 wdt->wcr = 0; /* disable watchdog */ 308 309 /* set timeout and enable watchdog */ 310 wdt->wmr = 311 ((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1; 312 wdt->wsr = 0x5555; /* reset watchdog counter */ 313 wdt->wsr = 0xAAAA; 314 315 puts("WATCHDOG:enabled\n"); 316 return (0); 317 } 318 #endif /* #ifdef CONFIG_WATCHDOG */ 319 320 #endif /* #ifdef CONFIG_M5275 */ 321 322 #ifdef CONFIG_M5282 323 int checkcpu(void) 324 { 325 unsigned char resetsource = MCFRESET_RSR; 326 327 printf("CPU: Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n", 328 MCFCCM_CIR >> 8, MCFCCM_CIR & MCFCCM_CIR_PRN_MASK); 329 printf("Reset:%s%s%s%s%s%s%s\n", 330 (resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "", 331 (resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "", 332 (resetsource & MCFRESET_RSR_EXT) ? " External" : "", 333 (resetsource & MCFRESET_RSR_POR) ? " Power On" : "", 334 (resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "", 335 (resetsource & MCFRESET_RSR_SOFT) ? " Software" : "", 336 (resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : ""); 337 return 0; 338 } 339 340 int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[]) 341 { 342 MCFRESET_RCR = MCFRESET_RCR_SOFTRST; 343 return 0; 344 }; 345 #endif 346 347 #ifdef CONFIG_M5249 348 int checkcpu(void) 349 { 350 char buf[32]; 351 352 printf("CPU: Freescale Coldfire MCF5249 at %s MHz\n", 353 strmhz(buf, CONFIG_SYS_CLK)); 354 return 0; 355 } 356 357 int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[]) 358 { 359 /* enable watchdog, set timeout to 0 and wait */ 360 mbar_writeByte(MCFSIM_SYPCR, 0xc0); 361 while (1) ; 362 363 /* we don't return! */ 364 return 0; 365 }; 366 #endif 367 368 #ifdef CONFIG_M5253 369 int checkcpu(void) 370 { 371 char buf[32]; 372 373 unsigned char resetsource = mbar_readLong(SIM_RSR); 374 printf("CPU: Freescale Coldfire MCF5253 at %s MHz\n", 375 strmhz(buf, CONFIG_SYS_CLK)); 376 377 if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) { 378 printf("Reset:%s%s\n", 379 (resetsource & SIM_RSR_HRST) ? " Hardware/ System Reset" 380 : "", 381 (resetsource & SIM_RSR_SWTR) ? " Software Watchdog" : 382 ""); 383 } 384 return 0; 385 } 386 387 int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[]) 388 { 389 /* enable watchdog, set timeout to 0 and wait */ 390 mbar_writeByte(SIM_SYPCR, 0xc0); 391 while (1) ; 392 393 /* we don't return! */ 394 return 0; 395 }; 396 #endif 397 398 #if defined(CONFIG_MCFFEC) 399 /* Default initializations for MCFFEC controllers. To override, 400 * create a board-specific function called: 401 * int board_eth_init(bd_t *bis) 402 */ 403 404 int cpu_eth_init(bd_t *bis) 405 { 406 return mcffec_initialize(bis); 407 } 408 #endif 409