1 /* 2 * (C) Copyright 2003 3 * Josef Baumgartner <josef.baumgartner@telex.de> 4 * 5 * MCF5282 additionals 6 * (C) Copyright 2005 7 * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de> 8 * 9 * MCF5275 additions 10 * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com) 11 * 12 * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. 13 * 14 * See file CREDITS for list of people who contributed to this 15 * project. 16 * 17 * This program is free software; you can redistribute it and/or 18 * modify it under the terms of the GNU General Public License as 19 * published by the Free Software Foundation; either version 2 of 20 * the License, or (at your option) any later version. 21 * 22 * This program is distributed in the hope that it will be useful, 23 * but WITHOUT ANY WARRANTY; without even the implied warranty of 24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 25 * GNU General Public License for more details. 26 * 27 * You should have received a copy of the GNU General Public License 28 * along with this program; if not, write to the Free Software 29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 30 * MA 02111-1307 USA 31 */ 32 33 #include <common.h> 34 #include <watchdog.h> 35 #include <command.h> 36 #include <asm/immap.h> 37 #include <asm/io.h> 38 #include <netdev.h> 39 #include "cpu.h" 40 41 DECLARE_GLOBAL_DATA_PTR; 42 43 #ifdef CONFIG_M5208 44 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 45 { 46 rcm_t *rcm = (rcm_t *)(MMAP_RCM); 47 48 udelay(1000); 49 50 out_8(&rcm->rcr, RCM_RCR_SOFTRST); 51 52 /* we don't return! */ 53 return 0; 54 }; 55 56 int checkcpu(void) 57 { 58 char buf1[32], buf2[32]; 59 60 printf("CPU: Freescale Coldfire MCF5208\n" 61 " CPU CLK %s MHz BUS CLK %s MHz\n", 62 strmhz(buf1, gd->cpu_clk), 63 strmhz(buf2, gd->bus_clk)); 64 return 0; 65 }; 66 67 #if defined(CONFIG_WATCHDOG) 68 /* Called by macro WATCHDOG_RESET */ 69 void watchdog_reset(void) 70 { 71 wdog_t *wdt = (wdog_t *)(MMAP_WDOG); 72 73 out_be16(&wdt->sr, 0x5555); 74 out_be16(&wdt->sr, 0xaaaa); 75 } 76 77 int watchdog_disable(void) 78 { 79 wdog_t *wdt = (wdog_t *)(MMAP_WDOG); 80 81 /* reset watchdog counter */ 82 out_be16(&wdt->sr, 0x5555); 83 out_be16(&wdt->sr, 0xaaaa); 84 /* disable watchdog timer */ 85 out_be16(&wdt->cr, 0); 86 87 puts("WATCHDOG:disabled\n"); 88 return (0); 89 } 90 91 int watchdog_init(void) 92 { 93 wdog_t *wdt = (wdog_t *)(MMAP_WDOG); 94 95 /* disable watchdog */ 96 out_be16(&wdt->cr, 0); 97 98 /* set timeout and enable watchdog */ 99 out_be16(&wdt->mr, 100 (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1); 101 102 /* reset watchdog counter */ 103 out_be16(&wdt->sr, 0x5555); 104 out_be16(&wdt->sr, 0xaaaa); 105 106 puts("WATCHDOG:enabled\n"); 107 return (0); 108 } 109 #endif /* #ifdef CONFIG_WATCHDOG */ 110 #endif /* #ifdef CONFIG_M5208 */ 111 112 #ifdef CONFIG_M5271 113 /* 114 * Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to 115 * determine which one we are running on, based on the Chip Identification 116 * Register (CIR). 117 */ 118 int checkcpu(void) 119 { 120 char buf[32]; 121 unsigned short cir; /* Chip Identification Register */ 122 unsigned short pin; /* Part identification number */ 123 unsigned char prn; /* Part revision number */ 124 char *cpu_model; 125 126 cir = mbar_readShort(MCF_CCM_CIR); 127 pin = cir >> MCF_CCM_CIR_PIN_LEN; 128 prn = cir & MCF_CCM_CIR_PRN_MASK; 129 130 switch (pin) { 131 case MCF_CCM_CIR_PIN_MCF5270: 132 cpu_model = "5270"; 133 break; 134 case MCF_CCM_CIR_PIN_MCF5271: 135 cpu_model = "5271"; 136 break; 137 default: 138 cpu_model = NULL; 139 break; 140 } 141 142 if (cpu_model) 143 printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n", 144 cpu_model, prn, strmhz(buf, CONFIG_SYS_CLK)); 145 else 146 printf("CPU: Unknown - Freescale ColdFire MCF5271 family" 147 " (PIN: 0x%x) rev. %hu, at %s MHz\n", 148 pin, prn, strmhz(buf, CONFIG_SYS_CLK)); 149 150 return 0; 151 } 152 153 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 154 { 155 /* Call the board specific reset actions first. */ 156 if(board_reset) { 157 board_reset(); 158 } 159 160 mbar_writeByte(MCF_RCM_RCR, 161 MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT); 162 return 0; 163 }; 164 165 #if defined(CONFIG_WATCHDOG) 166 void watchdog_reset(void) 167 { 168 mbar_writeShort(MCF_WTM_WSR, 0x5555); 169 mbar_writeShort(MCF_WTM_WSR, 0xAAAA); 170 } 171 172 int watchdog_disable(void) 173 { 174 mbar_writeShort(MCF_WTM_WCR, 0); 175 return (0); 176 } 177 178 int watchdog_init(void) 179 { 180 mbar_writeShort(MCF_WTM_WCR, MCF_WTM_WCR_EN); 181 return (0); 182 } 183 #endif /* #ifdef CONFIG_WATCHDOG */ 184 185 #endif 186 187 #ifdef CONFIG_M5272 188 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 189 { 190 wdog_t *wdp = (wdog_t *) (MMAP_WDOG); 191 192 out_be16(&wdp->wdog_wrrr, 0); 193 udelay(1000); 194 195 /* enable watchdog, set timeout to 0 and wait */ 196 out_be16(&wdp->wdog_wrrr, 1); 197 while (1) ; 198 199 /* we don't return! */ 200 return 0; 201 }; 202 203 int checkcpu(void) 204 { 205 sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG); 206 uchar msk; 207 char *suf; 208 209 puts("CPU: "); 210 msk = (in_be32(&sysctrl->sc_dir) > 28) & 0xf; 211 switch (msk) { 212 case 0x2: 213 suf = "1K75N"; 214 break; 215 case 0x4: 216 suf = "3K75N"; 217 break; 218 default: 219 suf = NULL; 220 printf("Freescale MCF5272 (Mask:%01x)\n", msk); 221 break; 222 } 223 224 if (suf) 225 printf("Freescale MCF5272 %s\n", suf); 226 return 0; 227 }; 228 229 #if defined(CONFIG_WATCHDOG) 230 /* Called by macro WATCHDOG_RESET */ 231 void watchdog_reset(void) 232 { 233 wdog_t *wdt = (wdog_t *)(MMAP_WDOG); 234 235 out_be16(&wdt->wdog_wcr, 0); 236 } 237 238 int watchdog_disable(void) 239 { 240 wdog_t *wdt = (wdog_t *)(MMAP_WDOG); 241 242 /* reset watchdog counter */ 243 out_be16(&wdt->wdog_wcr, 0); 244 /* disable watchdog interrupt */ 245 out_be16(&wdt->wdog_wirr, 0); 246 /* disable watchdog timer */ 247 out_be16(&wdt->wdog_wrrr, 0); 248 249 puts("WATCHDOG:disabled\n"); 250 return (0); 251 } 252 253 int watchdog_init(void) 254 { 255 wdog_t *wdt = (wdog_t *)(MMAP_WDOG); 256 257 /* disable watchdog interrupt */ 258 out_be16(&wdt->wdog_wirr, 0); 259 260 /* set timeout and enable watchdog */ 261 out_be16(&wdt->wdog_wrrr, 262 (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1); 263 264 /* reset watchdog counter */ 265 out_be16(&wdt->wdog_wcr, 0); 266 267 puts("WATCHDOG:enabled\n"); 268 return (0); 269 } 270 #endif /* #ifdef CONFIG_WATCHDOG */ 271 272 #endif /* #ifdef CONFIG_M5272 */ 273 274 #ifdef CONFIG_M5275 275 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 276 { 277 rcm_t *rcm = (rcm_t *)(MMAP_RCM); 278 279 udelay(1000); 280 281 out_8(&rcm->rcr, RCM_RCR_SOFTRST); 282 283 /* we don't return! */ 284 return 0; 285 }; 286 287 int checkcpu(void) 288 { 289 char buf[32]; 290 291 printf("CPU: Freescale Coldfire MCF5275 at %s MHz\n", 292 strmhz(buf, CONFIG_SYS_CLK)); 293 return 0; 294 }; 295 296 297 #if defined(CONFIG_WATCHDOG) 298 /* Called by macro WATCHDOG_RESET */ 299 void watchdog_reset(void) 300 { 301 wdog_t *wdt = (wdog_t *)(MMAP_WDOG); 302 303 out_be16(&wdt->wsr, 0x5555); 304 out_be16(&wdt->wsr, 0xaaaa); 305 } 306 307 int watchdog_disable(void) 308 { 309 wdog_t *wdt = (wdog_t *)(MMAP_WDOG); 310 311 /* reset watchdog counter */ 312 out_be16(&wdt->wsr, 0x5555); 313 out_be16(&wdt->wsr, 0xaaaa); 314 315 /* disable watchdog timer */ 316 out_be16(&wdt->wcr, 0); 317 318 puts("WATCHDOG:disabled\n"); 319 return (0); 320 } 321 322 int watchdog_init(void) 323 { 324 wdog_t *wdt = (wdog_t *)(MMAP_WDOG); 325 326 /* disable watchdog */ 327 out_be16(&wdt->wcr, 0); 328 329 /* set timeout and enable watchdog */ 330 out_be16(&wdt->wmr, 331 (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1); 332 333 /* reset watchdog counter */ 334 out_be16(&wdt->wsr, 0x5555); 335 out_be16(&wdt->wsr, 0xaaaa); 336 337 puts("WATCHDOG:enabled\n"); 338 return (0); 339 } 340 #endif /* #ifdef CONFIG_WATCHDOG */ 341 342 #endif /* #ifdef CONFIG_M5275 */ 343 344 #ifdef CONFIG_M5282 345 int checkcpu(void) 346 { 347 unsigned char resetsource = MCFRESET_RSR; 348 349 printf("CPU: Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n", 350 MCFCCM_CIR >> 8, MCFCCM_CIR & MCFCCM_CIR_PRN_MASK); 351 printf("Reset:%s%s%s%s%s%s%s\n", 352 (resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "", 353 (resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "", 354 (resetsource & MCFRESET_RSR_EXT) ? " External" : "", 355 (resetsource & MCFRESET_RSR_POR) ? " Power On" : "", 356 (resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "", 357 (resetsource & MCFRESET_RSR_SOFT) ? " Software" : "", 358 (resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : ""); 359 return 0; 360 } 361 362 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 363 { 364 MCFRESET_RCR = MCFRESET_RCR_SOFTRST; 365 return 0; 366 }; 367 #endif 368 369 #ifdef CONFIG_M5249 370 int checkcpu(void) 371 { 372 char buf[32]; 373 374 printf("CPU: Freescale Coldfire MCF5249 at %s MHz\n", 375 strmhz(buf, CONFIG_SYS_CLK)); 376 return 0; 377 } 378 379 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 380 { 381 /* enable watchdog, set timeout to 0 and wait */ 382 mbar_writeByte(MCFSIM_SYPCR, 0xc0); 383 while (1) ; 384 385 /* we don't return! */ 386 return 0; 387 }; 388 #endif 389 390 #ifdef CONFIG_M5253 391 int checkcpu(void) 392 { 393 char buf[32]; 394 395 unsigned char resetsource = mbar_readLong(SIM_RSR); 396 printf("CPU: Freescale Coldfire MCF5253 at %s MHz\n", 397 strmhz(buf, CONFIG_SYS_CLK)); 398 399 if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) { 400 printf("Reset:%s%s\n", 401 (resetsource & SIM_RSR_HRST) ? " Hardware/ System Reset" 402 : "", 403 (resetsource & SIM_RSR_SWTR) ? " Software Watchdog" : 404 ""); 405 } 406 return 0; 407 } 408 409 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 410 { 411 /* enable watchdog, set timeout to 0 and wait */ 412 mbar_writeByte(SIM_SYPCR, 0xc0); 413 while (1) ; 414 415 /* we don't return! */ 416 return 0; 417 }; 418 #endif 419 420 #if defined(CONFIG_MCFFEC) 421 /* Default initializations for MCFFEC controllers. To override, 422 * create a board-specific function called: 423 * int board_eth_init(bd_t *bis) 424 */ 425 426 int cpu_eth_init(bd_t *bis) 427 { 428 return mcffec_initialize(bis); 429 } 430 #endif 431