1 /* 2 * (C) Copyright 2003 3 * Josef Baumgartner <josef.baumgartner@telex.de> 4 * 5 * MCF5282 additionals 6 * (C) Copyright 2005 7 * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de> 8 * 9 * MCF5275 additions 10 * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com) 11 * 12 * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. 13 * 14 * SPDX-License-Identifier: GPL-2.0+ 15 */ 16 17 #include <common.h> 18 #include <watchdog.h> 19 #include <command.h> 20 #include <asm/immap.h> 21 #include <asm/io.h> 22 #include <netdev.h> 23 #include "cpu.h" 24 25 DECLARE_GLOBAL_DATA_PTR; 26 27 #ifdef CONFIG_M5208 28 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 29 { 30 rcm_t *rcm = (rcm_t *)(MMAP_RCM); 31 32 udelay(1000); 33 34 out_8(&rcm->rcr, RCM_RCR_SOFTRST); 35 36 /* we don't return! */ 37 return 0; 38 }; 39 40 #if defined(CONFIG_DISPLAY_CPUINFO) 41 int print_cpuinfo(void) 42 { 43 char buf1[32], buf2[32]; 44 45 printf("CPU: Freescale Coldfire MCF5208\n" 46 " CPU CLK %s MHz BUS CLK %s MHz\n", 47 strmhz(buf1, gd->cpu_clk), 48 strmhz(buf2, gd->bus_clk)); 49 return 0; 50 }; 51 #endif /* CONFIG_DISPLAY_CPUINFO */ 52 53 #if defined(CONFIG_WATCHDOG) 54 /* Called by macro WATCHDOG_RESET */ 55 void watchdog_reset(void) 56 { 57 wdog_t *wdt = (wdog_t *)(MMAP_WDOG); 58 59 out_be16(&wdt->sr, 0x5555); 60 out_be16(&wdt->sr, 0xaaaa); 61 } 62 63 int watchdog_disable(void) 64 { 65 wdog_t *wdt = (wdog_t *)(MMAP_WDOG); 66 67 /* reset watchdog counter */ 68 out_be16(&wdt->sr, 0x5555); 69 out_be16(&wdt->sr, 0xaaaa); 70 /* disable watchdog timer */ 71 out_be16(&wdt->cr, 0); 72 73 puts("WATCHDOG:disabled\n"); 74 return (0); 75 } 76 77 int watchdog_init(void) 78 { 79 wdog_t *wdt = (wdog_t *)(MMAP_WDOG); 80 81 /* disable watchdog */ 82 out_be16(&wdt->cr, 0); 83 84 /* set timeout and enable watchdog */ 85 out_be16(&wdt->mr, 86 (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1); 87 88 /* reset watchdog counter */ 89 out_be16(&wdt->sr, 0x5555); 90 out_be16(&wdt->sr, 0xaaaa); 91 92 puts("WATCHDOG:enabled\n"); 93 return (0); 94 } 95 #endif /* #ifdef CONFIG_WATCHDOG */ 96 #endif /* #ifdef CONFIG_M5208 */ 97 98 #ifdef CONFIG_M5271 99 #if defined(CONFIG_DISPLAY_CPUINFO) 100 /* 101 * Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to 102 * determine which one we are running on, based on the Chip Identification 103 * Register (CIR). 104 */ 105 int print_cpuinfo(void) 106 { 107 char buf[32]; 108 unsigned short cir; /* Chip Identification Register */ 109 unsigned short pin; /* Part identification number */ 110 unsigned char prn; /* Part revision number */ 111 char *cpu_model; 112 113 cir = mbar_readShort(MCF_CCM_CIR); 114 pin = cir >> MCF_CCM_CIR_PIN_LEN; 115 prn = cir & MCF_CCM_CIR_PRN_MASK; 116 117 switch (pin) { 118 case MCF_CCM_CIR_PIN_MCF5270: 119 cpu_model = "5270"; 120 break; 121 case MCF_CCM_CIR_PIN_MCF5271: 122 cpu_model = "5271"; 123 break; 124 default: 125 cpu_model = NULL; 126 break; 127 } 128 129 if (cpu_model) 130 printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n", 131 cpu_model, prn, strmhz(buf, CONFIG_SYS_CLK)); 132 else 133 printf("CPU: Unknown - Freescale ColdFire MCF5271 family" 134 " (PIN: 0x%x) rev. %hu, at %s MHz\n", 135 pin, prn, strmhz(buf, CONFIG_SYS_CLK)); 136 137 return 0; 138 } 139 #endif /* CONFIG_DISPLAY_CPUINFO */ 140 141 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 142 { 143 /* Call the board specific reset actions first. */ 144 if(board_reset) { 145 board_reset(); 146 } 147 148 mbar_writeByte(MCF_RCM_RCR, 149 MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT); 150 return 0; 151 }; 152 153 #if defined(CONFIG_WATCHDOG) 154 void watchdog_reset(void) 155 { 156 mbar_writeShort(MCF_WTM_WSR, 0x5555); 157 mbar_writeShort(MCF_WTM_WSR, 0xAAAA); 158 } 159 160 int watchdog_disable(void) 161 { 162 mbar_writeShort(MCF_WTM_WCR, 0); 163 return (0); 164 } 165 166 int watchdog_init(void) 167 { 168 mbar_writeShort(MCF_WTM_WCR, MCF_WTM_WCR_EN); 169 return (0); 170 } 171 #endif /* #ifdef CONFIG_WATCHDOG */ 172 173 #endif 174 175 #ifdef CONFIG_M5272 176 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 177 { 178 wdog_t *wdp = (wdog_t *) (MMAP_WDOG); 179 180 out_be16(&wdp->wdog_wrrr, 0); 181 udelay(1000); 182 183 /* enable watchdog, set timeout to 0 and wait */ 184 out_be16(&wdp->wdog_wrrr, 1); 185 while (1) ; 186 187 /* we don't return! */ 188 return 0; 189 }; 190 191 #if defined(CONFIG_DISPLAY_CPUINFO) 192 int print_cpuinfo(void) 193 { 194 sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG); 195 uchar msk; 196 char *suf; 197 198 puts("CPU: "); 199 msk = (in_be32(&sysctrl->sc_dir) > 28) & 0xf; 200 switch (msk) { 201 case 0x2: 202 suf = "1K75N"; 203 break; 204 case 0x4: 205 suf = "3K75N"; 206 break; 207 default: 208 suf = NULL; 209 printf("Freescale MCF5272 (Mask:%01x)\n", msk); 210 break; 211 } 212 213 if (suf) 214 printf("Freescale MCF5272 %s\n", suf); 215 return 0; 216 }; 217 #endif /* CONFIG_DISPLAY_CPUINFO */ 218 219 #if defined(CONFIG_WATCHDOG) 220 /* Called by macro WATCHDOG_RESET */ 221 void watchdog_reset(void) 222 { 223 wdog_t *wdt = (wdog_t *)(MMAP_WDOG); 224 225 out_be16(&wdt->wdog_wcr, 0); 226 } 227 228 int watchdog_disable(void) 229 { 230 wdog_t *wdt = (wdog_t *)(MMAP_WDOG); 231 232 /* reset watchdog counter */ 233 out_be16(&wdt->wdog_wcr, 0); 234 /* disable watchdog interrupt */ 235 out_be16(&wdt->wdog_wirr, 0); 236 /* disable watchdog timer */ 237 out_be16(&wdt->wdog_wrrr, 0); 238 239 puts("WATCHDOG:disabled\n"); 240 return (0); 241 } 242 243 int watchdog_init(void) 244 { 245 wdog_t *wdt = (wdog_t *)(MMAP_WDOG); 246 247 /* disable watchdog interrupt */ 248 out_be16(&wdt->wdog_wirr, 0); 249 250 /* set timeout and enable watchdog */ 251 out_be16(&wdt->wdog_wrrr, 252 (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1); 253 254 /* reset watchdog counter */ 255 out_be16(&wdt->wdog_wcr, 0); 256 257 puts("WATCHDOG:enabled\n"); 258 return (0); 259 } 260 #endif /* #ifdef CONFIG_WATCHDOG */ 261 262 #endif /* #ifdef CONFIG_M5272 */ 263 264 #ifdef CONFIG_M5275 265 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 266 { 267 rcm_t *rcm = (rcm_t *)(MMAP_RCM); 268 269 udelay(1000); 270 271 out_8(&rcm->rcr, RCM_RCR_SOFTRST); 272 273 /* we don't return! */ 274 return 0; 275 }; 276 277 #if defined(CONFIG_DISPLAY_CPUINFO) 278 int print_cpuinfo(void) 279 { 280 char buf[32]; 281 282 printf("CPU: Freescale Coldfire MCF5275 at %s MHz\n", 283 strmhz(buf, CONFIG_SYS_CLK)); 284 return 0; 285 }; 286 #endif /* CONFIG_DISPLAY_CPUINFO */ 287 288 #if defined(CONFIG_WATCHDOG) 289 /* Called by macro WATCHDOG_RESET */ 290 void watchdog_reset(void) 291 { 292 wdog_t *wdt = (wdog_t *)(MMAP_WDOG); 293 294 out_be16(&wdt->wsr, 0x5555); 295 out_be16(&wdt->wsr, 0xaaaa); 296 } 297 298 int watchdog_disable(void) 299 { 300 wdog_t *wdt = (wdog_t *)(MMAP_WDOG); 301 302 /* reset watchdog counter */ 303 out_be16(&wdt->wsr, 0x5555); 304 out_be16(&wdt->wsr, 0xaaaa); 305 306 /* disable watchdog timer */ 307 out_be16(&wdt->wcr, 0); 308 309 puts("WATCHDOG:disabled\n"); 310 return (0); 311 } 312 313 int watchdog_init(void) 314 { 315 wdog_t *wdt = (wdog_t *)(MMAP_WDOG); 316 317 /* disable watchdog */ 318 out_be16(&wdt->wcr, 0); 319 320 /* set timeout and enable watchdog */ 321 out_be16(&wdt->wmr, 322 (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1); 323 324 /* reset watchdog counter */ 325 out_be16(&wdt->wsr, 0x5555); 326 out_be16(&wdt->wsr, 0xaaaa); 327 328 puts("WATCHDOG:enabled\n"); 329 return (0); 330 } 331 #endif /* #ifdef CONFIG_WATCHDOG */ 332 333 #endif /* #ifdef CONFIG_M5275 */ 334 335 #ifdef CONFIG_M5282 336 #if defined(CONFIG_DISPLAY_CPUINFO) 337 int print_cpuinfo(void) 338 { 339 unsigned char resetsource = MCFRESET_RSR; 340 341 printf("CPU: Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n", 342 MCFCCM_CIR >> 8, MCFCCM_CIR & MCFCCM_CIR_PRN_MASK); 343 printf("Reset:%s%s%s%s%s%s%s\n", 344 (resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "", 345 (resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "", 346 (resetsource & MCFRESET_RSR_EXT) ? " External" : "", 347 (resetsource & MCFRESET_RSR_POR) ? " Power On" : "", 348 (resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "", 349 (resetsource & MCFRESET_RSR_SOFT) ? " Software" : "", 350 (resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : ""); 351 return 0; 352 } 353 #endif /* CONFIG_DISPLAY_CPUINFO */ 354 355 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 356 { 357 MCFRESET_RCR = MCFRESET_RCR_SOFTRST; 358 return 0; 359 }; 360 #endif 361 362 #ifdef CONFIG_M5249 363 #if defined(CONFIG_DISPLAY_CPUINFO) 364 int print_cpuinfo(void) 365 { 366 char buf[32]; 367 368 printf("CPU: Freescale Coldfire MCF5249 at %s MHz\n", 369 strmhz(buf, CONFIG_SYS_CLK)); 370 return 0; 371 } 372 #endif /* CONFIG_DISPLAY_CPUINFO */ 373 374 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 375 { 376 /* enable watchdog, set timeout to 0 and wait */ 377 mbar_writeByte(MCFSIM_SYPCR, 0xc0); 378 while (1) ; 379 380 /* we don't return! */ 381 return 0; 382 }; 383 #endif 384 385 #ifdef CONFIG_M5253 386 #if defined(CONFIG_DISPLAY_CPUINFO) 387 int print_cpuinfo(void) 388 { 389 char buf[32]; 390 391 unsigned char resetsource = mbar_readLong(SIM_RSR); 392 printf("CPU: Freescale Coldfire MCF5253 at %s MHz\n", 393 strmhz(buf, CONFIG_SYS_CLK)); 394 395 if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) { 396 printf("Reset:%s%s\n", 397 (resetsource & SIM_RSR_HRST) ? " Hardware/ System Reset" 398 : "", 399 (resetsource & SIM_RSR_SWTR) ? " Software Watchdog" : 400 ""); 401 } 402 return 0; 403 } 404 #endif /* CONFIG_DISPLAY_CPUINFO */ 405 406 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 407 { 408 /* enable watchdog, set timeout to 0 and wait */ 409 mbar_writeByte(SIM_SYPCR, 0xc0); 410 while (1) ; 411 412 /* we don't return! */ 413 return 0; 414 }; 415 #endif 416 417 #if defined(CONFIG_MCFFEC) 418 /* Default initializations for MCFFEC controllers. To override, 419 * create a board-specific function called: 420 * int board_eth_init(bd_t *bis) 421 */ 422 423 int cpu_eth_init(bd_t *bis) 424 { 425 return mcffec_initialize(bis); 426 } 427 #endif 428