1 /* 2 * (C) Copyright 2003 3 * Josef Baumgartner <josef.baumgartner@telex.de> 4 * 5 * MCF5282 additionals 6 * (C) Copyright 2005 7 * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de> 8 * 9 * MCF5275 additions 10 * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com) 11 * 12 * See file CREDITS for list of people who contributed to this 13 * project. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of 18 * the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 28 * MA 02111-1307 USA 29 */ 30 31 #include <common.h> 32 #include <watchdog.h> 33 #include <command.h> 34 #include <asm/immap.h> 35 #include <netdev.h> 36 #include "cpu.h" 37 38 DECLARE_GLOBAL_DATA_PTR; 39 40 #ifdef CONFIG_M5208 41 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 42 { 43 volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM); 44 45 udelay(1000); 46 47 rcm->rcr = RCM_RCR_SOFTRST; 48 49 /* we don't return! */ 50 return 0; 51 }; 52 53 int checkcpu(void) 54 { 55 char buf1[32], buf2[32]; 56 57 printf("CPU: Freescale Coldfire MCF5208\n" 58 " CPU CLK %s MHz BUS CLK %s MHz\n", 59 strmhz(buf1, gd->cpu_clk), 60 strmhz(buf2, gd->bus_clk)); 61 return 0; 62 }; 63 64 #if defined(CONFIG_WATCHDOG) 65 /* Called by macro WATCHDOG_RESET */ 66 void watchdog_reset(void) 67 { 68 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); 69 wdt->sr = 0x5555; 70 wdt->sr = 0xAAAA; 71 } 72 73 int watchdog_disable(void) 74 { 75 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); 76 77 wdt->sr = 0x5555; /* reset watchdog counter */ 78 wdt->sr = 0xAAAA; 79 wdt->cr = 0; /* disable watchdog timer */ 80 81 puts("WATCHDOG:disabled\n"); 82 return (0); 83 } 84 85 int watchdog_init(void) 86 { 87 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); 88 89 wdt->cr = 0; /* disable watchdog */ 90 91 /* set timeout and enable watchdog */ 92 wdt->mr = 93 ((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1; 94 wdt->sr = 0x5555; /* reset watchdog counter */ 95 wdt->sr = 0xAAAA; 96 97 puts("WATCHDOG:enabled\n"); 98 return (0); 99 } 100 #endif /* #ifdef CONFIG_WATCHDOG */ 101 #endif /* #ifdef CONFIG_M5208 */ 102 103 #ifdef CONFIG_M5271 104 /* 105 * Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to 106 * determine which one we are running on, based on the Chip Identification 107 * Register (CIR). 108 */ 109 int checkcpu(void) 110 { 111 char buf[32]; 112 unsigned short cir; /* Chip Identification Register */ 113 unsigned short pin; /* Part identification number */ 114 unsigned char prn; /* Part revision number */ 115 char *cpu_model; 116 117 cir = mbar_readShort(MCF_CCM_CIR); 118 pin = cir >> MCF_CCM_CIR_PIN_LEN; 119 prn = cir & MCF_CCM_CIR_PRN_MASK; 120 121 switch (pin) { 122 case MCF_CCM_CIR_PIN_MCF5270: 123 cpu_model = "5270"; 124 break; 125 case MCF_CCM_CIR_PIN_MCF5271: 126 cpu_model = "5271"; 127 break; 128 default: 129 cpu_model = NULL; 130 break; 131 } 132 133 if (cpu_model) 134 printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n", 135 cpu_model, prn, strmhz(buf, CONFIG_SYS_CLK)); 136 else 137 printf("CPU: Unknown - Freescale ColdFire MCF5271 family" 138 " (PIN: 0x%x) rev. %hu, at %s MHz\n", 139 pin, prn, strmhz(buf, CONFIG_SYS_CLK)); 140 141 return 0; 142 } 143 144 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 145 { 146 /* Call the board specific reset actions first. */ 147 if(board_reset) { 148 board_reset(); 149 } 150 151 mbar_writeByte(MCF_RCM_RCR, 152 MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT); 153 return 0; 154 }; 155 156 #if defined(CONFIG_WATCHDOG) 157 void watchdog_reset(void) 158 { 159 mbar_writeShort(MCF_WTM_WSR, 0x5555); 160 mbar_writeShort(MCF_WTM_WSR, 0xAAAA); 161 } 162 163 int watchdog_disable(void) 164 { 165 mbar_writeShort(MCF_WTM_WCR, 0); 166 return (0); 167 } 168 169 int watchdog_init(void) 170 { 171 mbar_writeShort(MCF_WTM_WCR, MCF_WTM_WCR_EN); 172 return (0); 173 } 174 #endif /* #ifdef CONFIG_WATCHDOG */ 175 176 #endif 177 178 #ifdef CONFIG_M5272 179 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 180 { 181 volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG); 182 183 wdp->wdog_wrrr = 0; 184 udelay(1000); 185 186 /* enable watchdog, set timeout to 0 and wait */ 187 wdp->wdog_wrrr = 1; 188 while (1) ; 189 190 /* we don't return! */ 191 return 0; 192 }; 193 194 int checkcpu(void) 195 { 196 volatile sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG); 197 uchar msk; 198 char *suf; 199 200 puts("CPU: "); 201 msk = (sysctrl->sc_dir > 28) & 0xf; 202 switch (msk) { 203 case 0x2: 204 suf = "1K75N"; 205 break; 206 case 0x4: 207 suf = "3K75N"; 208 break; 209 default: 210 suf = NULL; 211 printf("Freescale MCF5272 (Mask:%01x)\n", msk); 212 break; 213 } 214 215 if (suf) 216 printf("Freescale MCF5272 %s\n", suf); 217 return 0; 218 }; 219 220 #if defined(CONFIG_WATCHDOG) 221 /* Called by macro WATCHDOG_RESET */ 222 void watchdog_reset(void) 223 { 224 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); 225 wdt->wdog_wcr = 0; 226 } 227 228 int watchdog_disable(void) 229 { 230 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); 231 232 wdt->wdog_wcr = 0; /* reset watchdog counter */ 233 wdt->wdog_wirr = 0; /* disable watchdog interrupt */ 234 wdt->wdog_wrrr = 0; /* disable watchdog timer */ 235 236 puts("WATCHDOG:disabled\n"); 237 return (0); 238 } 239 240 int watchdog_init(void) 241 { 242 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); 243 244 wdt->wdog_wirr = 0; /* disable watchdog interrupt */ 245 246 /* set timeout and enable watchdog */ 247 wdt->wdog_wrrr = 248 ((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1; 249 wdt->wdog_wcr = 0; /* reset watchdog counter */ 250 251 puts("WATCHDOG:enabled\n"); 252 return (0); 253 } 254 #endif /* #ifdef CONFIG_WATCHDOG */ 255 256 #endif /* #ifdef CONFIG_M5272 */ 257 258 #ifdef CONFIG_M5275 259 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 260 { 261 volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM); 262 263 udelay(1000); 264 265 rcm->rcr = RCM_RCR_SOFTRST; 266 267 /* we don't return! */ 268 return 0; 269 }; 270 271 int checkcpu(void) 272 { 273 char buf[32]; 274 275 printf("CPU: Freescale Coldfire MCF5275 at %s MHz\n", 276 strmhz(buf, CONFIG_SYS_CLK)); 277 return 0; 278 }; 279 280 281 #if defined(CONFIG_WATCHDOG) 282 /* Called by macro WATCHDOG_RESET */ 283 void watchdog_reset(void) 284 { 285 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); 286 wdt->wsr = 0x5555; 287 wdt->wsr = 0xAAAA; 288 } 289 290 int watchdog_disable(void) 291 { 292 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); 293 294 wdt->wsr = 0x5555; /* reset watchdog counter */ 295 wdt->wsr = 0xAAAA; 296 wdt->wcr = 0; /* disable watchdog timer */ 297 298 puts("WATCHDOG:disabled\n"); 299 return (0); 300 } 301 302 int watchdog_init(void) 303 { 304 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); 305 306 wdt->wcr = 0; /* disable watchdog */ 307 308 /* set timeout and enable watchdog */ 309 wdt->wmr = 310 ((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1; 311 wdt->wsr = 0x5555; /* reset watchdog counter */ 312 wdt->wsr = 0xAAAA; 313 314 puts("WATCHDOG:enabled\n"); 315 return (0); 316 } 317 #endif /* #ifdef CONFIG_WATCHDOG */ 318 319 #endif /* #ifdef CONFIG_M5275 */ 320 321 #ifdef CONFIG_M5282 322 int checkcpu(void) 323 { 324 unsigned char resetsource = MCFRESET_RSR; 325 326 printf("CPU: Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n", 327 MCFCCM_CIR >> 8, MCFCCM_CIR & MCFCCM_CIR_PRN_MASK); 328 printf("Reset:%s%s%s%s%s%s%s\n", 329 (resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "", 330 (resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "", 331 (resetsource & MCFRESET_RSR_EXT) ? " External" : "", 332 (resetsource & MCFRESET_RSR_POR) ? " Power On" : "", 333 (resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "", 334 (resetsource & MCFRESET_RSR_SOFT) ? " Software" : "", 335 (resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : ""); 336 return 0; 337 } 338 339 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 340 { 341 MCFRESET_RCR = MCFRESET_RCR_SOFTRST; 342 return 0; 343 }; 344 #endif 345 346 #ifdef CONFIG_M5249 347 int checkcpu(void) 348 { 349 char buf[32]; 350 351 printf("CPU: Freescale Coldfire MCF5249 at %s MHz\n", 352 strmhz(buf, CONFIG_SYS_CLK)); 353 return 0; 354 } 355 356 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 357 { 358 /* enable watchdog, set timeout to 0 and wait */ 359 mbar_writeByte(MCFSIM_SYPCR, 0xc0); 360 while (1) ; 361 362 /* we don't return! */ 363 return 0; 364 }; 365 #endif 366 367 #ifdef CONFIG_M5253 368 int checkcpu(void) 369 { 370 char buf[32]; 371 372 unsigned char resetsource = mbar_readLong(SIM_RSR); 373 printf("CPU: Freescale Coldfire MCF5253 at %s MHz\n", 374 strmhz(buf, CONFIG_SYS_CLK)); 375 376 if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) { 377 printf("Reset:%s%s\n", 378 (resetsource & SIM_RSR_HRST) ? " Hardware/ System Reset" 379 : "", 380 (resetsource & SIM_RSR_SWTR) ? " Software Watchdog" : 381 ""); 382 } 383 return 0; 384 } 385 386 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 387 { 388 /* enable watchdog, set timeout to 0 and wait */ 389 mbar_writeByte(SIM_SYPCR, 0xc0); 390 while (1) ; 391 392 /* we don't return! */ 393 return 0; 394 }; 395 #endif 396 397 #if defined(CONFIG_MCFFEC) 398 /* Default initializations for MCFFEC controllers. To override, 399 * create a board-specific function called: 400 * int board_eth_init(bd_t *bis) 401 */ 402 403 int cpu_eth_init(bd_t *bis) 404 { 405 return mcffec_initialize(bis); 406 } 407 #endif 408