1 /* 2 * 3 * (C) Copyright 2000-2003 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 * 6 * (C) Copyright 2007, 2012 Freescale Semiconductor, Inc. 7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 #include <watchdog.h> 14 #include <asm/immap.h> 15 #include <asm/io.h> 16 17 #if defined(CONFIG_CMD_NET) 18 #include <config.h> 19 #include <net.h> 20 #include <asm/fec.h> 21 #endif 22 23 /* 24 * Breath some life into the CPU... 25 * 26 * Set up the memory map, 27 * initialize a bunch of registers, 28 * initialize the UPM's 29 */ 30 void cpu_init_f(void) 31 { 32 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 33 fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; 34 wdog_t *wdog = (wdog_t *) MMAP_WDOG; 35 scm_t *scm = (scm_t *) MMAP_SCM; 36 37 /* watchdog is enabled by default - disable the watchdog */ 38 #ifndef CONFIG_WATCHDOG 39 out_be16(&wdog->cr, 0); 40 #endif 41 42 out_be32(&scm->rambar, CONFIG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE); 43 44 /* Port configuration */ 45 out_8(&gpio->par_cs, 0); 46 47 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL)) 48 out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); 49 out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); 50 out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); 51 #endif 52 53 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL)) 54 setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS1); 55 out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); 56 out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); 57 out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); 58 #endif 59 60 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL)) 61 setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS2); 62 out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); 63 out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); 64 out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); 65 #endif 66 67 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL)) 68 setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS3); 69 out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); 70 out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); 71 out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); 72 #endif 73 74 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL)) 75 setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS4); 76 out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE); 77 out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL); 78 out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK); 79 #endif 80 81 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL)) 82 setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS5); 83 out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE); 84 out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL); 85 out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK); 86 #endif 87 88 #if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) && defined(CONFIG_SYS_CS6_CTRL)) 89 setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS6); 90 out_be32(&fbcs->csar6, CONFIG_SYS_CS6_BASE); 91 out_be32(&fbcs->cscr6, CONFIG_SYS_CS6_CTRL); 92 out_be32(&fbcs->csmr6, CONFIG_SYS_CS6_MASK); 93 #endif 94 95 #if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) && defined(CONFIG_SYS_CS7_CTRL)) 96 setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS7); 97 out_be32(&fbcs->csar7, CONFIG_SYS_CS7_BASE); 98 out_be32(&fbcs->cscr7, CONFIG_SYS_CS7_CTRL); 99 out_be32(&fbcs->csmr7, CONFIG_SYS_CS7_MASK); 100 #endif 101 102 #ifdef CONFIG_SYS_I2C_FSL 103 CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR; 104 CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET; 105 #endif 106 107 icache_enable(); 108 } 109 110 /* 111 * initialize higher level parts of CPU like timers 112 */ 113 int cpu_init_r(void) 114 { 115 return (0); 116 } 117 118 void uart_port_conf(int port) 119 { 120 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 121 122 /* Setup Ports: */ 123 switch (port) { 124 case 0: 125 clrbits_be16(&gpio->par_uart, 126 GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD); 127 setbits_be16(&gpio->par_uart, 128 GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD); 129 break; 130 case 1: 131 clrbits_be16(&gpio->par_uart, 132 GPIO_PAR_UART_U1RXD_MASK | GPIO_PAR_UART_U1TXD_MASK); 133 setbits_be16(&gpio->par_uart, 134 GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD); 135 break; 136 case 2: 137 #ifdef CONFIG_SYS_UART2_PRI_GPIO 138 clrbits_be16(&gpio->par_uart, 139 GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD); 140 setbits_be16(&gpio->par_uart, 141 GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD); 142 #elif defined(CONFIG_SYS_UART2_ALT1_GPIO) 143 clrbits_8(&gpio->par_feci2c, 144 GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK); 145 setbits_8(&gpio->par_feci2c, 146 GPIO_PAR_FECI2C_EMDC_U2TXD | GPIO_PAR_FECI2C_EMDIO_U2RXD); 147 #endif 148 break; 149 } 150 } 151 152 #if defined(CONFIG_CMD_NET) 153 int fecpin_setclear(struct eth_device *dev, int setclear) 154 { 155 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 156 157 if (setclear) { 158 setbits_8(&gpio->par_feci2c, 159 GPIO_PAR_FECI2C_EMDC_FECEMDC | 160 GPIO_PAR_FECI2C_EMDIO_FECEMDIO); 161 } else { 162 clrbits_8(&gpio->par_feci2c, 163 GPIO_PAR_FECI2C_EMDC_MASK | 164 GPIO_PAR_FECI2C_EMDIO_MASK); 165 } 166 167 return 0; 168 } 169 #endif 170