xref: /openbmc/u-boot/arch/m68k/cpu/mcf5227x/start.S (revision ca6c5e03) 
1/*
2 * Copyright (C) 2003	Josef Baumgartner <josef.baumgartner@telex.de>
3 * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
4 *
5 * SPDX-License-Identifier:	GPL-2.0+
6 */
7
8#include <asm-offsets.h>
9#include <config.h>
10#include "version.h"
11#include <asm/cache.h>
12
13#ifndef	 CONFIG_IDENT_STRING
14#define	 CONFIG_IDENT_STRING ""
15#endif
16
17#define _START	_start
18#define _FAULT	_fault
19
20#define SAVE_ALL						\
21	move.w	#0x2700,%sr;		/* disable intrs */	\
22	subl	#60,%sp;		/* space for 15 regs */ \
23	moveml	%d0-%d7/%a0-%a6,%sp@;
24
25#define RESTORE_ALL						\
26	moveml	%sp@,%d0-%d7/%a0-%a6;				\
27	addl	#60,%sp;		/* space for 15 regs */ \
28	rte;
29
30#if defined(CONFIG_CF_SBF)
31#define ASM_DRAMINIT	(asm_dram_init - CONFIG_SYS_TEXT_BASE + \
32	CONFIG_SYS_INIT_RAM_ADDR)
33#define ASM_SBF_IMG_HDR	(asm_sbf_img_hdr - CONFIG_SYS_TEXT_BASE + \
34	CONFIG_SYS_INIT_RAM_ADDR)
35#endif
36
37.text
38
39/*
40 * Vector table. This is used for initial platform startup.
41 * These vectors are to catch any un-intended traps.
42 */
43_vectors:
44#if defined(CONFIG_CF_SBF)
45INITSP:	.long	0			/* Initial SP	*/
46INITPC:	.long	ASM_DRAMINIT		/* Initial PC 	*/
47#else
48INITSP:	.long	0			/* Initial SP	*/
49INITPC:	.long	_START			/* Initial PC 	*/
50#endif
51
52vector02_0F:
53.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
54.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
55
56/* Reserved */
57vector10_17:
58.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
59
60vector18_1F:
61.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
62
63#if !defined(CONFIG_CF_SBF)
64/* TRAP #0 - #15 */
65vector20_2F:
66.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
67.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
68
69/* Reserved	*/
70vector30_3F:
71.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
72.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
73
74vector64_127:
75.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
76.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
77.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
78.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
79.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
80.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
81.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
82.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
83
84vector128_191:
85.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
86.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
87.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
88.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
89.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
90.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
91.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
92.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
93
94vector192_255:
95.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
96.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
97.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
98.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
99.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
100.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
101.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
102.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
103#endif
104
105#if defined(CONFIG_CF_SBF)
106	/* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */
107asm_sbf_img_hdr:
108	.long	0x00000000		/* checksum, not yet implemented */
109	.long	0x00020000		/* image length */
110	.long	CONFIG_SYS_TEXT_BASE	/* image to be relocated at */
111
112asm_dram_init:
113	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
114	movec	%d0, %RAMBAR1		/* init Rambar */
115
116	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
117	clr.l	%sp@-
118
119	/* Must disable global address */
120	move.l	#0xFC008000, %a1
121	move.l	#(CONFIG_SYS_CS0_BASE), (%a1)
122	move.l	#0xFC008008, %a1
123	move.l	#(CONFIG_SYS_CS0_CTRL), (%a1)
124	move.l	#0xFC008004, %a1
125	move.l	#(CONFIG_SYS_CS0_MASK), (%a1)
126
127	/*
128	 * Dram Initialization
129	 * a1, a2, and d0
130	 */
131	move.l	#0xFC0A4074, %a1
132	move.b	#(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
133	nop
134
135	/* SDRAM Chip 0 and 1 */
136	move.l	#0xFC0B8110, %a1
137	move.l	#0xFC0B8114, %a2
138
139	/* calculate the size */
140	move.l	#0x13, %d1
141	move.l	#(CONFIG_SYS_SDRAM_SIZE), %d2
142#ifdef CONFIG_SYS_SDRAM_BASE1
143	lsr.l	#1, %d2
144#endif
145
146dramsz_loop:
147	lsr.l	#1, %d2
148	add.l	#1, %d1
149	cmp.l	#1, %d2
150	bne	dramsz_loop
151
152	/* SDRAM Chip 0 and 1 */
153	move.l	#(CONFIG_SYS_SDRAM_BASE), (%a1)
154	or.l	%d1, (%a1)
155#ifdef CONFIG_SYS_SDRAM_BASE1
156	move.l	#(CONFIG_SYS_SDRAM_BASE1), (%a2)
157	or.l	%d1, (%a2)
158#endif
159	nop
160
161	/* dram cfg1 and cfg2 */
162	move.l	#0xFC0B8008, %a1
163	move.l	#(CONFIG_SYS_SDRAM_CFG1), (%a1)
164	nop
165	move.l	#0xFC0B800C, %a2
166	move.l	#(CONFIG_SYS_SDRAM_CFG2), (%a2)
167	nop
168
169	move.l	#0xFC0B8000, %a1	/* Mode */
170	move.l	#0xFC0B8004, %a2	/* Ctrl */
171
172	/* Issue PALL */
173	move.l	#(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
174	nop
175
176	/* Issue LEMR */
177	move.l	#(CONFIG_SYS_SDRAM_MODE), (%a1)
178	nop
179	move.l	#(CONFIG_SYS_SDRAM_EMOD), (%a1)
180	nop
181
182	move.l	#1000, %d0
183wait1000:
184	nop
185	subq.l	#1, %d0
186	bne	wait1000
187
188	/* Issue PALL */
189	move.l	#(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
190	nop
191
192	/* Perform two refresh cycles */
193	move.l	#(CONFIG_SYS_SDRAM_CTRL + 4), %d0
194	nop
195	move.l	%d0, (%a2)
196	move.l	%d0, (%a2)
197	nop
198
199	move.l	#(CONFIG_SYS_SDRAM_CTRL), %d0
200	and.l	#0x7FFFFFFF, %d0
201	or.l	#0x10000c00, %d0
202	move.l	%d0, (%a2)
203	nop
204
205	/*
206	 * DSPI Initialization
207	 * a0 - general, sram - 0x80008000 - 32, see M52277EVB.h
208	 * a1 - dspi status
209	 * a2 - dtfr
210	 * a3 - drfr
211	 * a4 - Dst addr
212	 */
213
214	/* Enable pins for DSPI mode - chip-selects are enabled later */
215	move.l	#0xFC0A4036, %a0
216	move.b	#0x3F, %d0
217	move.b	%d0, (%a0)
218
219	/* DSPI CS */
220#ifdef CONFIG_SYS_DSPI_CS0
221	move.b	(%a0), %d0
222	or.l	#0xC0, %d0
223	move.b	%d0, (%a0)
224#endif
225#ifdef CONFIG_SYS_DSPI_CS2
226	move.l	#0xFC0A4037, %a0
227	move.b	(%a0), %d0
228	or.l	#0x10, %d0
229	move.b	%d0, (%a0)
230#endif
231	nop
232
233	/* Configure DSPI module */
234	move.l	#0xFC05C000, %a0
235	move.l	#0x80FF0C00, (%a0)	/* Master, clear TX/RX FIFO */
236
237	move.l	#0xFC05C00C, %a0
238	move.l	#0x3E000011, (%a0)
239
240	move.l	#0xFC05C034, %a2	/* dtfr */
241	move.l	#0xFC05C03B, %a3	/* drfr */
242
243	move.l	#(ASM_SBF_IMG_HDR + 4), %a1
244	move.l	(%a1)+, %d5
245	move.l	(%a1), %a4
246
247	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_SBFHDR_DATA_OFFSET), %a0
248	move.l	#(CONFIG_SYS_SBFHDR_SIZE), %d4
249
250	move.l	#0xFC05C02C, %a1	/* dspi status */
251
252	/* Issue commands and address */
253	move.l	#0x8004000B, %d2	/* Fast Read Cmd */
254	jsr	asm_dspi_wr_status
255	jsr	asm_dspi_rd_status
256
257	move.l	#0x80040000, %d2	/* Address byte 2 */
258	jsr	asm_dspi_wr_status
259	jsr	asm_dspi_rd_status
260
261	move.l	#0x80040000, %d2	/* Address byte 1 */
262	jsr	asm_dspi_wr_status
263	jsr	asm_dspi_rd_status
264
265	move.l	#0x80040000, %d2	/* Address byte 0 */
266	jsr	asm_dspi_wr_status
267	jsr	asm_dspi_rd_status
268
269	move.l	#0x80040000, %d2	/* Dummy Wr and Rd */
270	jsr	asm_dspi_wr_status
271	jsr	asm_dspi_rd_status
272
273	/* Transfer serial boot header to sram */
274asm_dspi_rd_loop1:
275	move.l	#0x80040000, %d2
276	jsr	asm_dspi_wr_status
277	jsr	asm_dspi_rd_status
278
279	move.b	%d1, (%a0)		/* read, copy to dst */
280
281	add.l	#1, %a0			/* inc dst by 1 */
282	sub.l	#1, %d4			/* dec cnt by 1 */
283	bne	asm_dspi_rd_loop1
284
285	/* Transfer u-boot from serial flash to memory */
286asm_dspi_rd_loop2:
287	move.l	#0x80040000, %d2
288	jsr	asm_dspi_wr_status
289	jsr	asm_dspi_rd_status
290
291	move.b	%d1, (%a4)		/* read, copy to dst */
292
293	add.l	#1, %a4			/* inc dst by 1 */
294	sub.l	#1, %d5			/* dec cnt by 1 */
295	bne	asm_dspi_rd_loop2
296
297	move.l	#0x00040000, %d2	/* Terminate */
298	jsr	asm_dspi_wr_status
299	jsr	asm_dspi_rd_status
300
301	/* jump to memory and execute */
302	move.l	#(CONFIG_SYS_TEXT_BASE + 0x400), %a0
303	move.l	%a0, (%a1)
304	jmp	(%a0)
305
306asm_dspi_wr_status:
307	move.l	(%a1), %d0		/* status */
308	and.l	#0x0000F000, %d0
309	cmp.l	#0x00003000, %d0
310	bgt	asm_dspi_wr_status
311
312	move.l	%d2, (%a2)
313	rts
314
315asm_dspi_rd_status:
316	move.l	(%a1), %d0		/* status */
317	and.l	#0x000000F0, %d0
318	lsr.l	#4, %d0
319	cmp.l	#0, %d0
320	beq	asm_dspi_rd_status
321
322	move.b	(%a3), %d1
323	rts
324#endif /* CONFIG_CF_SBF */
325
326.text
327	. = 0x400
328.globl _start
329_start:
330	nop
331	nop
332	move.w	#0x2700,%sr		/* Mask off Interrupt */
333
334	/* Set vector base register at the beginning of the Flash */
335#if defined(CONFIG_CF_SBF)
336	move.l	#CONFIG_SYS_TEXT_BASE, %d0
337	movec	%d0, %VBR
338#else
339	move.l	#CONFIG_SYS_FLASH_BASE, %d0
340	movec	%d0, %VBR
341
342	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
343	movec	%d0, %RAMBAR1
344#endif
345
346	/* invalidate and disable cache */
347	move.l	#CF_CACR_CINV, %d0	/* Invalidate cache cmd */
348	movec	%d0, %CACR		/* Invalidate cache */
349	move.l	#0, %d0
350	movec	%d0, %ACR0
351	movec	%d0, %ACR1
352
353	/* initialize general use internal ram */
354	move.l	#0, %d0
355	move.l	#(ICACHE_STATUS), %a1	/* icache */
356	move.l	#(DCACHE_STATUS), %a2	/* icache */
357	move.l	%d0, (%a1)
358	move.l	%d0, (%a2)
359
360	/* put relocation table address to a5 */
361	move.l	#__got_start, %a5
362
363	/* setup stack initially on top of internal static ram  */
364	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
365
366	/*
367	 * if configured, malloc_f arena will be reserved first,
368	 * then (and always) gd struct space will be reserved
369	 */
370	move.l	%sp, -(%sp)
371	bsr	board_init_f_alloc_reserve
372
373	/* update stack and frame-pointers */
374	move.l	%d0, %sp
375	move.l	%sp, %fp
376
377	/* initialize reserved area */
378	move.l	%d0, -(%sp)
379	bsr	board_init_f_init_reserve
380
381	/* run low-level CPU init code (from flash) */
382	bsr	cpu_init_f
383	clr.l	%sp@-
384
385	/* run low-level board init code (from flash) */
386	bsr	board_init_f
387
388	/* board_init_f() does not return */
389
390/******************************************************************************/
391
392/*
393 * void relocate_code (addr_sp, gd, addr_moni)
394 *
395 * This "function" does not return, instead it continues in RAM
396 * after relocating the monitor code.
397 *
398 * r3 = dest
399 * r4 = src
400 * r5 = length in bytes
401 * r6 = cachelinesize
402 */
403.globl relocate_code
404relocate_code:
405	link.w	%a6,#0
406	move.l	8(%a6), %sp		/* set new stack pointer */
407
408	move.l	12(%a6), %d0		/* Save copy of Global Data pointer */
409	move.l	16(%a6), %a0		/* Save copy of Destination Address */
410
411	move.l	#CONFIG_SYS_MONITOR_BASE, %a1
412	move.l	#__init_end, %a2
413	move.l	%a0, %a3
414
415	/* copy the code to RAM */
4161:
417	move.l	(%a1)+, (%a3)+
418	cmp.l	%a1,%a2
419	bgt.s	1b
420
421/*
422 * We are done. Do not return, instead branch to second part of board
423 * initialization, now running from RAM.
424 */
425	move.l	%a0, %a1
426	add.l	#(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
427	jmp	(%a1)
428
429in_ram:
430
431clear_bss:
432	/*
433	 * Now clear BSS segment
434	 */
435	move.l	%a0, %a1
436	add.l	#(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
437	move.l	%a0, %d1
438	add.l	#(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
4396:
440	clr.l	(%a1)+
441	cmp.l	%a1,%d1
442	bgt.s	6b
443
444	/*
445	 * fix got table in RAM
446	 */
447	move.l	%a0, %a1
448	add.l	#(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
449	move.l	%a1,%a5			/* fix got pointer register a5 */
450
451	move.l	%a0, %a2
452	add.l	#(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
453
4547:
455	move.l	(%a1),%d1
456	sub.l	#_start,%d1
457	add.l	%a0,%d1
458	move.l	%d1,(%a1)+
459	cmp.l	%a2, %a1
460	bne	7b
461
462	/* calculate relative jump to board_init_r in ram */
463	move.l	%a0, %a1
464	add.l	#(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
465
466	/* set parameters for board_init_r */
467	move.l	%a0,-(%sp)		/* dest_addr */
468	move.l	%d0,-(%sp)		/* gd */
469	jsr	(%a1)
470
471/******************************************************************************/
472
473/* exception code */
474.globl _fault
475_fault:
476	bra	_fault
477
478.globl _exc_handler
479_exc_handler:
480	SAVE_ALL
481	movel	%sp,%sp@-
482	bsr	exc_handler
483	addql	#4,%sp
484	RESTORE_ALL
485
486.globl _int_handler
487_int_handler:
488	SAVE_ALL
489	movel	%sp,%sp@-
490	bsr	int_handler
491	addql	#4,%sp
492	RESTORE_ALL
493
494/******************************************************************************/
495
496.globl version_string
497version_string:
498.ascii U_BOOT_VERSION_STRING, "\0"
499.align 4
500