1 /* 2 * 3 * (C) Copyright 2000-2003 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 * 6 * (C) Copyright 2004-2007, 2012 Freescale Semiconductor, Inc. 7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #include <common.h> 29 #include <watchdog.h> 30 31 #include <asm/immap.h> 32 #include <asm/io.h> 33 #include <asm/rtc.h> 34 35 /* 36 * Breath some life into the CPU... 37 * 38 * Set up the memory map, 39 * initialize a bunch of registers, 40 * initialize the UPM's 41 */ 42 void cpu_init_f(void) 43 { 44 scm1_t *scm1 = (scm1_t *) MMAP_SCM1; 45 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 46 fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; 47 pll_t *pll = (pll_t *)MMAP_PLL; 48 49 #if !defined(CONFIG_CF_SBF) 50 /* Workaround, must place before fbcs */ 51 out_be32(&pll->psr, 0x12); 52 53 out_be32(&scm1->mpr, 0x77777777); 54 out_be32(&scm1->pacra, 0); 55 out_be32(&scm1->pacrb, 0); 56 out_be32(&scm1->pacrc, 0); 57 out_be32(&scm1->pacrd, 0); 58 out_be32(&scm1->pacre, 0); 59 out_be32(&scm1->pacrf, 0); 60 out_be32(&scm1->pacrg, 0); 61 out_be32(&scm1->pacri, 0); 62 63 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ 64 && defined(CONFIG_SYS_CS0_CTRL)) 65 out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); 66 out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); 67 out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); 68 #endif 69 #endif /* CONFIG_CF_SBF */ 70 71 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ 72 && defined(CONFIG_SYS_CS1_CTRL)) 73 out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); 74 out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); 75 out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); 76 #endif 77 78 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ 79 && defined(CONFIG_SYS_CS2_CTRL)) 80 out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); 81 out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); 82 out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); 83 #endif 84 85 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ 86 && defined(CONFIG_SYS_CS3_CTRL)) 87 out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); 88 out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); 89 out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); 90 #endif 91 92 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ 93 && defined(CONFIG_SYS_CS4_CTRL)) 94 out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE); 95 out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL); 96 out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK); 97 #endif 98 99 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \ 100 && defined(CONFIG_SYS_CS5_CTRL)) 101 out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE); 102 out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL); 103 out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK); 104 #endif 105 106 #ifdef CONFIG_FSL_I2C 107 out_8(&gpio->par_i2c, GPIO_PAR_I2C_SCL_SCL | GPIO_PAR_I2C_SDA_SDA); 108 #endif 109 110 icache_enable(); 111 } 112 113 /* 114 * initialize higher level parts of CPU like timers 115 */ 116 int cpu_init_r(void) 117 { 118 #ifdef CONFIG_MCFRTC 119 rtc_t *rtc = (rtc_t *)(CONFIG_SYS_MCFRTC_BASE); 120 rtcex_t *rtcex = (rtcex_t *)&rtc->extended; 121 122 out_be32(&rtcex->gocu, (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xffff); 123 out_be32(&rtcex->gocl, CONFIG_SYS_RTC_OSCILLATOR & 0xffff); 124 #endif 125 126 return (0); 127 } 128 129 void uart_port_conf(int port) 130 { 131 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 132 133 /* Setup Ports: */ 134 switch (port) { 135 case 0: 136 clrbits_be16(&gpio->par_uart, 137 ~(GPIO_PAR_UART_U0TXD_UNMASK & GPIO_PAR_UART_U0RXD_UNMASK)); 138 setbits_be16(&gpio->par_uart, 139 GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD); 140 break; 141 case 1: 142 clrbits_be16(&gpio->par_uart, 143 ~(GPIO_PAR_UART_U1TXD_UNMASK & GPIO_PAR_UART_U1RXD_UNMASK)); 144 setbits_be16(&gpio->par_uart, 145 GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD); 146 break; 147 case 2: 148 clrbits_8(&gpio->par_dspi, 149 ~(GPIO_PAR_DSPI_SIN_UNMASK & GPIO_PAR_DSPI_SOUT_UNMASK)); 150 out_8(&gpio->par_dspi, 151 GPIO_PAR_DSPI_SIN_U2RXD | GPIO_PAR_DSPI_SOUT_U2TXD); 152 break; 153 } 154 } 155 156 #ifdef CONFIG_CF_DSPI 157 void cfspi_port_conf(void) 158 { 159 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 160 161 out_8(&gpio->par_dspi, 162 GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT | 163 GPIO_PAR_DSPI_SCK_SCK); 164 } 165 166 int cfspi_claim_bus(uint bus, uint cs) 167 { 168 dspi_t *dspi = (dspi_t *) MMAP_DSPI; 169 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 170 171 if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS) 172 return -1; 173 174 /* Clear FIFO and resume transfer */ 175 clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF); 176 177 switch (cs) { 178 case 0: 179 clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_UNMASK); 180 setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0); 181 break; 182 case 2: 183 clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK); 184 setbits_8(&gpio->par_timer, GPIO_PAR_TIMER_T2IN_DSPIPCS2); 185 break; 186 } 187 188 return 0; 189 } 190 191 void cfspi_release_bus(uint bus, uint cs) 192 { 193 dspi_t *dspi = (dspi_t *) MMAP_DSPI; 194 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 195 196 /* Clear FIFO */ 197 clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF); 198 199 switch (cs) { 200 case 0: 201 clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0); 202 break; 203 case 2: 204 clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK); 205 break; 206 } 207 } 208 #endif 209