1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * 4 * (C) Copyright 2000-2003 5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6 * 7 * (C) Copyright 2004-2007, 2012 Freescale Semiconductor, Inc. 8 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 9 */ 10 11 #include <common.h> 12 #include <watchdog.h> 13 14 #include <asm/immap.h> 15 #include <asm/io.h> 16 #include <asm/rtc.h> 17 #include <linux/compiler.h> 18 19 /* 20 * Breath some life into the CPU... 21 * 22 * Set up the memory map, 23 * initialize a bunch of registers, 24 * initialize the UPM's 25 */ 26 void cpu_init_f(void) 27 { 28 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 29 fbcs_t *fbcs __maybe_unused = (fbcs_t *) MMAP_FBCS; 30 31 #if !defined(CONFIG_CF_SBF) 32 scm1_t *scm1 = (scm1_t *) MMAP_SCM1; 33 pll_t *pll = (pll_t *)MMAP_PLL; 34 35 /* Workaround, must place before fbcs */ 36 out_be32(&pll->psr, 0x12); 37 38 out_be32(&scm1->mpr, 0x77777777); 39 out_be32(&scm1->pacra, 0); 40 out_be32(&scm1->pacrb, 0); 41 out_be32(&scm1->pacrc, 0); 42 out_be32(&scm1->pacrd, 0); 43 out_be32(&scm1->pacre, 0); 44 out_be32(&scm1->pacrf, 0); 45 out_be32(&scm1->pacrg, 0); 46 out_be32(&scm1->pacri, 0); 47 48 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ 49 && defined(CONFIG_SYS_CS0_CTRL)) 50 out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); 51 out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); 52 out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); 53 #endif 54 #endif /* CONFIG_CF_SBF */ 55 56 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ 57 && defined(CONFIG_SYS_CS1_CTRL)) 58 out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); 59 out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); 60 out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); 61 #endif 62 63 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ 64 && defined(CONFIG_SYS_CS2_CTRL)) 65 out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); 66 out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); 67 out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); 68 #endif 69 70 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ 71 && defined(CONFIG_SYS_CS3_CTRL)) 72 out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); 73 out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); 74 out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); 75 #endif 76 77 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ 78 && defined(CONFIG_SYS_CS4_CTRL)) 79 out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE); 80 out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL); 81 out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK); 82 #endif 83 84 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \ 85 && defined(CONFIG_SYS_CS5_CTRL)) 86 out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE); 87 out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL); 88 out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK); 89 #endif 90 91 #ifdef CONFIG_SYS_I2C_FSL 92 out_8(&gpio->par_i2c, GPIO_PAR_I2C_SCL_SCL | GPIO_PAR_I2C_SDA_SDA); 93 #endif 94 95 icache_enable(); 96 } 97 98 /* 99 * initialize higher level parts of CPU like timers 100 */ 101 int cpu_init_r(void) 102 { 103 #ifdef CONFIG_MCFRTC 104 rtc_t *rtc = (rtc_t *)(CONFIG_SYS_MCFRTC_BASE); 105 rtcex_t *rtcex = (rtcex_t *)&rtc->extended; 106 107 out_be32(&rtcex->gocu, (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xffff); 108 out_be32(&rtcex->gocl, CONFIG_SYS_RTC_OSCILLATOR & 0xffff); 109 #endif 110 111 return (0); 112 } 113 114 void uart_port_conf(int port) 115 { 116 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 117 118 /* Setup Ports: */ 119 switch (port) { 120 case 0: 121 clrbits_be16(&gpio->par_uart, 122 ~(GPIO_PAR_UART_U0TXD_UNMASK & GPIO_PAR_UART_U0RXD_UNMASK)); 123 setbits_be16(&gpio->par_uart, 124 GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD); 125 break; 126 case 1: 127 clrbits_be16(&gpio->par_uart, 128 ~(GPIO_PAR_UART_U1TXD_UNMASK & GPIO_PAR_UART_U1RXD_UNMASK)); 129 setbits_be16(&gpio->par_uart, 130 GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD); 131 break; 132 case 2: 133 clrbits_8(&gpio->par_dspi, 134 ~(GPIO_PAR_DSPI_SIN_UNMASK & GPIO_PAR_DSPI_SOUT_UNMASK)); 135 out_8(&gpio->par_dspi, 136 GPIO_PAR_DSPI_SIN_U2RXD | GPIO_PAR_DSPI_SOUT_U2TXD); 137 break; 138 } 139 } 140 141 #ifdef CONFIG_CF_DSPI 142 void cfspi_port_conf(void) 143 { 144 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 145 146 out_8(&gpio->par_dspi, 147 GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT | 148 GPIO_PAR_DSPI_SCK_SCK); 149 } 150 151 int cfspi_claim_bus(uint bus, uint cs) 152 { 153 dspi_t *dspi = (dspi_t *) MMAP_DSPI; 154 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 155 156 if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS) 157 return -1; 158 159 /* Clear FIFO and resume transfer */ 160 clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF); 161 162 switch (cs) { 163 case 0: 164 clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_UNMASK); 165 setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0); 166 break; 167 case 2: 168 clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK); 169 setbits_8(&gpio->par_timer, GPIO_PAR_TIMER_T2IN_DSPIPCS2); 170 break; 171 } 172 173 return 0; 174 } 175 176 void cfspi_release_bus(uint bus, uint cs) 177 { 178 dspi_t *dspi = (dspi_t *) MMAP_DSPI; 179 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 180 181 /* Clear FIFO */ 182 clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF); 183 184 switch (cs) { 185 case 0: 186 clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0); 187 break; 188 case 2: 189 clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK); 190 break; 191 } 192 } 193 #endif 194