1 /* 2 * 3 * (C) Copyright 2000-2003 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 * 6 * (C) Copyright 2004-2007, 2012 Freescale Semiconductor, Inc. 7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #include <common.h> 29 #include <watchdog.h> 30 31 #include <asm/immap.h> 32 #include <asm/io.h> 33 #include <asm/rtc.h> 34 #include <linux/compiler.h> 35 36 /* 37 * Breath some life into the CPU... 38 * 39 * Set up the memory map, 40 * initialize a bunch of registers, 41 * initialize the UPM's 42 */ 43 void cpu_init_f(void) 44 { 45 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 46 fbcs_t *fbcs __maybe_unused = (fbcs_t *) MMAP_FBCS; 47 48 #if !defined(CONFIG_CF_SBF) 49 scm1_t *scm1 = (scm1_t *) MMAP_SCM1; 50 pll_t *pll = (pll_t *)MMAP_PLL; 51 52 /* Workaround, must place before fbcs */ 53 out_be32(&pll->psr, 0x12); 54 55 out_be32(&scm1->mpr, 0x77777777); 56 out_be32(&scm1->pacra, 0); 57 out_be32(&scm1->pacrb, 0); 58 out_be32(&scm1->pacrc, 0); 59 out_be32(&scm1->pacrd, 0); 60 out_be32(&scm1->pacre, 0); 61 out_be32(&scm1->pacrf, 0); 62 out_be32(&scm1->pacrg, 0); 63 out_be32(&scm1->pacri, 0); 64 65 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ 66 && defined(CONFIG_SYS_CS0_CTRL)) 67 out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); 68 out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); 69 out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); 70 #endif 71 #endif /* CONFIG_CF_SBF */ 72 73 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ 74 && defined(CONFIG_SYS_CS1_CTRL)) 75 out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); 76 out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); 77 out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); 78 #endif 79 80 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ 81 && defined(CONFIG_SYS_CS2_CTRL)) 82 out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); 83 out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); 84 out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); 85 #endif 86 87 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ 88 && defined(CONFIG_SYS_CS3_CTRL)) 89 out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); 90 out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); 91 out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); 92 #endif 93 94 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ 95 && defined(CONFIG_SYS_CS4_CTRL)) 96 out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE); 97 out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL); 98 out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK); 99 #endif 100 101 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \ 102 && defined(CONFIG_SYS_CS5_CTRL)) 103 out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE); 104 out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL); 105 out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK); 106 #endif 107 108 #ifdef CONFIG_FSL_I2C 109 out_8(&gpio->par_i2c, GPIO_PAR_I2C_SCL_SCL | GPIO_PAR_I2C_SDA_SDA); 110 #endif 111 112 icache_enable(); 113 } 114 115 /* 116 * initialize higher level parts of CPU like timers 117 */ 118 int cpu_init_r(void) 119 { 120 #ifdef CONFIG_MCFRTC 121 rtc_t *rtc = (rtc_t *)(CONFIG_SYS_MCFRTC_BASE); 122 rtcex_t *rtcex = (rtcex_t *)&rtc->extended; 123 124 out_be32(&rtcex->gocu, (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xffff); 125 out_be32(&rtcex->gocl, CONFIG_SYS_RTC_OSCILLATOR & 0xffff); 126 #endif 127 128 return (0); 129 } 130 131 void uart_port_conf(int port) 132 { 133 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 134 135 /* Setup Ports: */ 136 switch (port) { 137 case 0: 138 clrbits_be16(&gpio->par_uart, 139 ~(GPIO_PAR_UART_U0TXD_UNMASK & GPIO_PAR_UART_U0RXD_UNMASK)); 140 setbits_be16(&gpio->par_uart, 141 GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD); 142 break; 143 case 1: 144 clrbits_be16(&gpio->par_uart, 145 ~(GPIO_PAR_UART_U1TXD_UNMASK & GPIO_PAR_UART_U1RXD_UNMASK)); 146 setbits_be16(&gpio->par_uart, 147 GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD); 148 break; 149 case 2: 150 clrbits_8(&gpio->par_dspi, 151 ~(GPIO_PAR_DSPI_SIN_UNMASK & GPIO_PAR_DSPI_SOUT_UNMASK)); 152 out_8(&gpio->par_dspi, 153 GPIO_PAR_DSPI_SIN_U2RXD | GPIO_PAR_DSPI_SOUT_U2TXD); 154 break; 155 } 156 } 157 158 #ifdef CONFIG_CF_DSPI 159 void cfspi_port_conf(void) 160 { 161 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 162 163 out_8(&gpio->par_dspi, 164 GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT | 165 GPIO_PAR_DSPI_SCK_SCK); 166 } 167 168 int cfspi_claim_bus(uint bus, uint cs) 169 { 170 dspi_t *dspi = (dspi_t *) MMAP_DSPI; 171 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 172 173 if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS) 174 return -1; 175 176 /* Clear FIFO and resume transfer */ 177 clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF); 178 179 switch (cs) { 180 case 0: 181 clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_UNMASK); 182 setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0); 183 break; 184 case 2: 185 clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK); 186 setbits_8(&gpio->par_timer, GPIO_PAR_TIMER_T2IN_DSPIPCS2); 187 break; 188 } 189 190 return 0; 191 } 192 193 void cfspi_release_bus(uint bus, uint cs) 194 { 195 dspi_t *dspi = (dspi_t *) MMAP_DSPI; 196 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 197 198 /* Clear FIFO */ 199 clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF); 200 201 switch (cs) { 202 case 0: 203 clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0); 204 break; 205 case 2: 206 clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK); 207 break; 208 } 209 } 210 #endif 211