xref: /openbmc/u-boot/arch/m68k/cpu/mcf5227x/cpu_init.c (revision 1e52fea3)
1 /*
2  *
3  * (C) Copyright 2000-2003
4  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5  *
6  * (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
7  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8  *
9  * See file CREDITS for list of people who contributed to this
10  * project.
11  *
12  * This program is free software; you can redistribute it and/or
13  * modify it under the terms of the GNU General Public License as
14  * published by the Free Software Foundation; either version 2 of
15  * the License, or (at your option) any later version.
16  *
17  * This program is distributed in the hope that it will be useful,
18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
20  * GNU General Public License for more details.
21  *
22  * You should have received a copy of the GNU General Public License
23  * along with this program; if not, write to the Free Software
24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25  * MA 02111-1307 USA
26  */
27 
28 #include <common.h>
29 #include <watchdog.h>
30 
31 #include <asm/immap.h>
32 #include <asm/rtc.h>
33 
34 /*
35  * Breath some life into the CPU...
36  *
37  * Set up the memory map,
38  * initialize a bunch of registers,
39  * initialize the UPM's
40  */
41 void cpu_init_f(void)
42 {
43 	volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
44 	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
45 	volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
46 	volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
47 
48 #if !defined(CONFIG_CF_SBF)
49 	/* Workaround, must place before fbcs */
50 	pll->psr = 0x12;
51 
52 	scm1->mpr = 0x77777777;
53 	scm1->pacra = 0;
54 	scm1->pacrb = 0;
55 	scm1->pacrc = 0;
56 	scm1->pacrd = 0;
57 	scm1->pacre = 0;
58 	scm1->pacrf = 0;
59 	scm1->pacrg = 0;
60 	scm1->pacri = 0;
61 
62 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
63      && defined(CONFIG_SYS_CS0_CTRL))
64 	fbcs->csar0 = CONFIG_SYS_CS0_BASE;
65 	fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
66 	fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
67 #endif
68 #endif				/* CONFIG_CF_SBF */
69 
70 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
71      && defined(CONFIG_SYS_CS1_CTRL))
72 	fbcs->csar1 = CONFIG_SYS_CS1_BASE;
73 	fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
74 	fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
75 #endif
76 
77 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
78      && defined(CONFIG_SYS_CS2_CTRL))
79 	fbcs->csar2 = CONFIG_SYS_CS2_BASE;
80 	fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
81 	fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
82 #endif
83 
84 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
85      && defined(CONFIG_SYS_CS3_CTRL))
86 	fbcs->csar3 = CONFIG_SYS_CS3_BASE;
87 	fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
88 	fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
89 #endif
90 
91 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
92      && defined(CONFIG_SYS_CS4_CTRL))
93 	fbcs->csar4 = CONFIG_SYS_CS4_BASE;
94 	fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
95 	fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
96 #endif
97 
98 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
99      && defined(CONFIG_SYS_CS5_CTRL))
100 	fbcs->csar5 = CONFIG_SYS_CS5_BASE;
101 	fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
102 	fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
103 #endif
104 
105 #ifdef CONFIG_FSL_I2C
106 	gpio->par_i2c = GPIO_PAR_I2C_SCL_SCL | GPIO_PAR_I2C_SDA_SDA;
107 #endif
108 
109 	icache_enable();
110 }
111 
112 /*
113  * initialize higher level parts of CPU like timers
114  */
115 int cpu_init_r(void)
116 {
117 #ifdef CONFIG_MCFRTC
118 	volatile rtc_t *rtc = (volatile rtc_t *)(CONFIG_SYS_MCFRTC_BASE);
119 	volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended;
120 
121 	rtcex->gocu = (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xFFFF;
122 	rtcex->gocl = CONFIG_SYS_RTC_OSCILLATOR & 0xFFFF;
123 #endif
124 
125 	return (0);
126 }
127 
128 void uart_port_conf(int port)
129 {
130 	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
131 
132 	/* Setup Ports: */
133 	switch (port) {
134 	case 0:
135 		gpio->par_uart &=
136 		    (GPIO_PAR_UART_U0TXD_UNMASK & GPIO_PAR_UART_U0RXD_UNMASK);
137 		gpio->par_uart |=
138 		    (GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
139 		break;
140 	case 1:
141 		gpio->par_uart &=
142 		    (GPIO_PAR_UART_U1TXD_UNMASK & GPIO_PAR_UART_U1RXD_UNMASK);
143 		gpio->par_uart |=
144 		    (GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
145 		break;
146 	case 2:
147 		gpio->par_dspi &=
148 		    (GPIO_PAR_DSPI_SIN_UNMASK & GPIO_PAR_DSPI_SOUT_UNMASK);
149 		gpio->par_dspi =
150 		    (GPIO_PAR_DSPI_SIN_U2RXD | GPIO_PAR_DSPI_SOUT_U2TXD);
151 		break;
152 	}
153 }
154 
155 #ifdef CONFIG_CF_DSPI
156 void cfspi_port_conf(void)
157 {
158 	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
159 
160 	gpio->par_dspi =
161 	    GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
162 	    GPIO_PAR_DSPI_SCK_SCK;
163 }
164 
165 int cfspi_claim_bus(uint bus, uint cs)
166 {
167 	volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
168 	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
169 
170 	if ((dspi->sr & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
171 		return -1;
172 
173 	/* Clear FIFO and resume transfer */
174 	dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF);
175 
176 	switch (cs) {
177 	case 0:
178 		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_UNMASK;
179 		gpio->par_dspi |= GPIO_PAR_DSPI_PCS0_PCS0;
180 		break;
181 	case 2:
182 		gpio->par_timer &= GPIO_PAR_TIMER_T2IN_UNMASK;
183 		gpio->par_timer |= GPIO_PAR_TIMER_T2IN_DSPIPCS2;
184 		break;
185 	}
186 
187 	return 0;
188 }
189 
190 void cfspi_release_bus(uint bus, uint cs)
191 {
192 	volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
193 	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
194 
195 	dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF);	/* Clear FIFO */
196 
197 	switch (cs) {
198 	case 0:
199 		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
200 		break;
201 	case 2:
202 		gpio->par_timer &= GPIO_PAR_TIMER_T2IN_UNMASK;
203 		break;
204 	}
205 }
206 #endif
207