1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2014 - 2015 Xilinx, Inc. 4 * Michal Simek <michal.simek@xilinx.com> 5 */ 6 7 #ifndef _ASM_ARCH_HARDWARE_H 8 #define _ASM_ARCH_HARDWARE_H 9 10 #define ZYNQ_I2C_BASEADDR0 0xFF020000 11 #define ZYNQ_I2C_BASEADDR1 0xFF030000 12 13 #define ARASAN_NAND_BASEADDR 0xFF100000 14 15 #define ZYNQMP_TCM_BASE_ADDR 0xFFE00000 16 #define ZYNQMP_TCM_SIZE 0x40000 17 18 #define ZYNQMP_CRL_APB_BASEADDR 0xFF5E0000 19 #define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1000000 20 #define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT 0 21 #define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT 8 22 23 #define PS_MODE0 BIT(0) 24 #define PS_MODE1 BIT(1) 25 #define PS_MODE2 BIT(2) 26 #define PS_MODE3 BIT(3) 27 28 #define RESET_REASON_DEBUG_SYS BIT(6) 29 #define RESET_REASON_SOFT BIT(5) 30 #define RESET_REASON_SRST BIT(4) 31 #define RESET_REASON_PSONLY BIT(3) 32 #define RESET_REASON_PMU BIT(2) 33 #define RESET_REASON_INTERNAL BIT(1) 34 #define RESET_REASON_EXTERNAL BIT(0) 35 36 struct crlapb_regs { 37 u32 reserved0[36]; 38 u32 cpu_r5_ctrl; /* 0x90 */ 39 u32 reserved1[37]; 40 u32 timestamp_ref_ctrl; /* 0x128 */ 41 u32 reserved2[53]; 42 u32 boot_mode; /* 0x200 */ 43 u32 reserved3_0[7]; 44 u32 reset_reason; /* 0x220 */ 45 u32 reserved3_1[6]; 46 u32 rst_lpd_top; /* 0x23C */ 47 u32 reserved4[4]; 48 u32 boot_pin_ctrl; /* 0x250 */ 49 u32 reserved5[21]; 50 }; 51 52 #define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR) 53 54 #define ZYNQMP_IOU_SCNTR_SECURE 0xFF260000 55 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN 0x1 56 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG 0x2 57 58 struct iou_scntr_secure { 59 u32 counter_control_register; 60 u32 reserved0[7]; 61 u32 base_frequency_id_register; 62 }; 63 64 #define iou_scntr_secure ((struct iou_scntr_secure *)ZYNQMP_IOU_SCNTR_SECURE) 65 66 /* Bootmode setting values */ 67 #define BOOT_MODES_MASK 0x0000000F 68 #define QSPI_MODE_24BIT 0x00000001 69 #define QSPI_MODE_32BIT 0x00000002 70 #define SD_MODE 0x00000003 /* sd 0 */ 71 #define SD_MODE1 0x00000005 /* sd 1 */ 72 #define NAND_MODE 0x00000004 73 #define EMMC_MODE 0x00000006 74 #define USB_MODE 0x00000007 75 #define SD1_LSHFT_MODE 0x0000000E /* SD1 Level shifter */ 76 #define JTAG_MODE 0x00000000 77 #define BOOT_MODE_USE_ALT 0x100 78 #define BOOT_MODE_ALT_SHIFT 12 79 /* SW secondary boot modes 0xa - 0xd */ 80 #define SW_USBHOST_MODE 0x0000000A 81 #define SW_SATA_MODE 0x0000000B 82 83 #define ZYNQMP_IOU_SLCR_BASEADDR 0xFF180000 84 85 struct iou_slcr_regs { 86 u32 mio_pin[78]; 87 u32 reserved[442]; 88 }; 89 90 #define slcr_base ((struct iou_slcr_regs *)ZYNQMP_IOU_SLCR_BASEADDR) 91 92 #define ZYNQMP_RPU_BASEADDR 0xFF9A0000 93 94 struct rpu_regs { 95 u32 rpu_glbl_ctrl; 96 u32 reserved0[63]; 97 u32 rpu0_cfg; /* 0x100 */ 98 u32 reserved1[63]; 99 u32 rpu1_cfg; /* 0x200 */ 100 }; 101 102 #define rpu_base ((struct rpu_regs *)ZYNQMP_RPU_BASEADDR) 103 104 #define ZYNQMP_CRF_APB_BASEADDR 0xFD1A0000 105 106 struct crfapb_regs { 107 u32 reserved0[65]; 108 u32 rst_fpd_apu; /* 0x104 */ 109 u32 reserved1; 110 }; 111 112 #define crfapb_base ((struct crfapb_regs *)ZYNQMP_CRF_APB_BASEADDR) 113 114 #define ZYNQMP_APU_BASEADDR 0xFD5C0000 115 116 struct apu_regs { 117 u32 reserved0[16]; 118 u32 rvbar_addr0_l; /* 0x40 */ 119 u32 rvbar_addr0_h; /* 0x44 */ 120 u32 reserved1[20]; 121 }; 122 123 #define apu_base ((struct apu_regs *)ZYNQMP_APU_BASEADDR) 124 125 /* Board version value */ 126 #define ZYNQMP_CSU_BASEADDR 0xFFCA0000 127 #define ZYNQMP_CSU_VERSION_SILICON 0x0 128 #define ZYNQMP_CSU_VERSION_QEMU 0x3 129 130 #define ZYNQMP_CSU_VERSION_EMPTY_SHIFT 20 131 132 #define ZYNQMP_SILICON_VER_MASK 0xF000 133 #define ZYNQMP_SILICON_VER_SHIFT 12 134 135 struct csu_regs { 136 u32 reserved0[17]; 137 u32 version; 138 }; 139 140 #define csu_base ((struct csu_regs *)ZYNQMP_CSU_BASEADDR) 141 142 #define ZYNQMP_PMU_BASEADDR 0xFFD80000 143 144 struct pmu_regs { 145 u32 reserved[18]; 146 u32 gen_storage6; /* 0x48 */ 147 }; 148 149 #define pmu_base ((struct pmu_regs *)ZYNQMP_PMU_BASEADDR) 150 151 #define ZYNQMP_CSU_IDCODE_ADDR 0xFFCA0040 152 #define ZYNQMP_CSU_VER_ADDR 0xFFCA0044 153 154 #endif /* _ASM_ARCH_HARDWARE_H */ 155