1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2012 Michal Simek <monstr@monstr.eu> 4 * Copyright (C) 2012 Xilinx, Inc. All rights reserved. 5 */ 6 #include <common.h> 7 #include <asm/io.h> 8 #include <asm/arch/clk.h> 9 #include <asm/arch/sys_proto.h> 10 #include <asm/arch/hardware.h> 11 12 #define ZYNQ_SILICON_VER_MASK 0xF0000000 13 #define ZYNQ_SILICON_VER_SHIFT 28 14 15 int arch_cpu_init(void) 16 { 17 zynq_slcr_unlock(); 18 #ifndef CONFIG_SPL_BUILD 19 /* Device config APB, unlock the PCAP */ 20 writel(0x757BDF0D, &devcfg_base->unlock); 21 writel(0xFFFFFFFF, &devcfg_base->rom_shadow); 22 23 #if (CONFIG_SYS_SDRAM_BASE == 0) 24 /* remap DDR to zero, FILTERSTART */ 25 writel(0, &scu_base->filter_start); 26 27 /* OCM_CFG, Mask out the ROM, map ram into upper addresses */ 28 writel(0x1F, &slcr_base->ocm_cfg); 29 /* FPGA_RST_CTRL, clear resets on AXI fabric ports */ 30 writel(0x0, &slcr_base->fpga_rst_ctrl); 31 /* Set urgent bits with register */ 32 writel(0x0, &slcr_base->ddr_urgent_sel); 33 /* Urgent write, ports S2/S3 */ 34 writel(0xC, &slcr_base->ddr_urgent); 35 #endif 36 #endif 37 zynq_slcr_lock(); 38 39 return 0; 40 } 41 42 unsigned int zynq_get_silicon_version(void) 43 { 44 return (readl(&devcfg_base->mctrl) & ZYNQ_SILICON_VER_MASK) 45 >> ZYNQ_SILICON_VER_SHIFT; 46 } 47 48 void reset_cpu(ulong addr) 49 { 50 zynq_slcr_cpu_reset(); 51 while (1) 52 ; 53 } 54 55 #ifndef CONFIG_SYS_DCACHE_OFF 56 void enable_caches(void) 57 { 58 /* Enable D-cache. I-cache is already enabled in start.S */ 59 dcache_enable(); 60 } 61 #endif 62