1*ec48b6c9SMichal Simek /* SPDX-License-Identifier: GPL-2.0+ */ 2*ec48b6c9SMichal Simek /* 3*ec48b6c9SMichal Simek * Copyright 2016 - 2018 Xilinx, Inc. 4*ec48b6c9SMichal Simek */ 5*ec48b6c9SMichal Simek 6*ec48b6c9SMichal Simek #define VERSAL_CRL_APB_BASEADDR 0xFF5E0000 7*ec48b6c9SMichal Simek 8*ec48b6c9SMichal Simek #define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT BIT(25) 9*ec48b6c9SMichal Simek 10*ec48b6c9SMichal Simek #define IOU_SWITCH_CTRL_CLKACT_BIT BIT(25) 11*ec48b6c9SMichal Simek #define IOU_SWITCH_CTRL_DIVISOR0_SHIFT 8 12*ec48b6c9SMichal Simek 13*ec48b6c9SMichal Simek struct crlapb_regs { 14*ec48b6c9SMichal Simek u32 reserved0[69]; 15*ec48b6c9SMichal Simek u32 iou_switch_ctrl; /* 0x114 */ 16*ec48b6c9SMichal Simek u32 reserved1[13]; 17*ec48b6c9SMichal Simek u32 timestamp_ref_ctrl; /* 0x14c */ 18*ec48b6c9SMichal Simek u32 reserved2[126]; 19*ec48b6c9SMichal Simek u32 rst_timestamp; /* 0x348 */ 20*ec48b6c9SMichal Simek }; 21*ec48b6c9SMichal Simek 22*ec48b6c9SMichal Simek #define crlapb_base ((struct crlapb_regs *)VERSAL_CRL_APB_BASEADDR) 23*ec48b6c9SMichal Simek 24*ec48b6c9SMichal Simek #define VERSAL_IOU_SCNTR_SECURE 0xFF140000 25*ec48b6c9SMichal Simek 26*ec48b6c9SMichal Simek #define IOU_SCNTRS_CONTROL_EN 1 27*ec48b6c9SMichal Simek 28*ec48b6c9SMichal Simek struct iou_scntrs_regs { 29*ec48b6c9SMichal Simek u32 counter_control_register; /* 0x0 */ 30*ec48b6c9SMichal Simek u32 reserved0[7]; 31*ec48b6c9SMichal Simek u32 base_frequency_id_register; /* 0x20 */ 32*ec48b6c9SMichal Simek }; 33*ec48b6c9SMichal Simek 34*ec48b6c9SMichal Simek #define iou_scntr_secure ((struct iou_scntrs_regs *)VERSAL_IOU_SCNTR_SECURE) 35