1 /* 2 * UniPhier SC (System Control) block registers for ARMv8 SoCs 3 * 4 * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef SC64_REGS_H 10 #define SC64_REGS_H 11 12 #define SC_BASE_ADDR 0x61840000 13 14 #define SC_RSTCTRL (SC_BASE_ADDR | 0x2000) 15 #define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008) 16 #define SC_RSTCTRL4 (SC_BASE_ADDR | 0x200c) 17 #define SC_RSTCTRL4_ETHER (1 << 6) 18 #define SC_RSTCTRL4_NAND (1 << 0) 19 #define SC_RSTCTRL5 (SC_BASE_ADDR | 0x2010) 20 #define SC_RSTCTRL6 (SC_BASE_ADDR | 0x2014) 21 #define SC_RSTCTRL7 (SC_BASE_ADDR | 0x2018) 22 #define SC_RSTCTRL7_UMCSB (1 << 16) 23 #define SC_RSTCTRL7_UMCA2 (1 << 10) 24 #define SC_RSTCTRL7_UMCA1 (1 << 9) 25 #define SC_RSTCTRL7_UMCA0 (1 << 8) 26 #define SC_RSTCTRL7_UMC32 (1 << 2) 27 #define SC_RSTCTRL7_UMC31 (1 << 1) 28 #define SC_RSTCTRL7_UMC30 (1 << 0) 29 30 #define SC_CLKCTRL (SC_BASE_ADDR | 0x2100) 31 #define SC_CLKCTRL3 (SC_BASE_ADDR | 0x2108) 32 #define SC_CLKCTRL4 (SC_BASE_ADDR | 0x210c) 33 #define SC_CLKCTRL4_PERI (1 << 7) 34 #define SC_CLKCTRL4_ETHER (1 << 6) 35 #define SC_CLKCTRL4_NAND (1 << 0) 36 #define SC_CLKCTRL5 (SC_BASE_ADDR | 0x2110) 37 #define SC_CLKCTRL6 (SC_BASE_ADDR | 0x2114) 38 #define SC_CLKCTRL7 (SC_BASE_ADDR | 0x2118) 39 #define SC_CLKCTRL7_UMCSB (1 << 16) 40 #define SC_CLKCTRL7_UMC32 (1 << 2) 41 #define SC_CLKCTRL7_UMC31 (1 << 1) 42 #define SC_CLKCTRL7_UMC30 (1 << 0) 43 44 #endif /* SC64_REGS_H */ 45