1 /* 2 * UniPhier SC (System Control) block registers for ARMv8 SoCs 3 * 4 * Copyright (C) 2016 Socionext Inc. 5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef SC64_REGS_H 11 #define SC64_REGS_H 12 13 #define SC_BASE_ADDR 0x61840000 14 15 #define SC_RSTCTRL (SC_BASE_ADDR | 0x2000) 16 #define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008) 17 #define SC_RSTCTRL4 (SC_BASE_ADDR | 0x200c) 18 #define SC_RSTCTRL4_ETHER (1 << 6) 19 #define SC_RSTCTRL4_NAND (1 << 0) 20 #define SC_RSTCTRL5 (SC_BASE_ADDR | 0x2010) 21 #define SC_RSTCTRL6 (SC_BASE_ADDR | 0x2014) 22 #define SC_RSTCTRL7 (SC_BASE_ADDR | 0x2018) 23 #define SC_RSTCTRL7_UMCSB (1 << 16) 24 #define SC_RSTCTRL7_UMCA2 (1 << 10) 25 #define SC_RSTCTRL7_UMCA1 (1 << 9) 26 #define SC_RSTCTRL7_UMCA0 (1 << 8) 27 #define SC_RSTCTRL7_UMC32 (1 << 2) 28 #define SC_RSTCTRL7_UMC31 (1 << 1) 29 #define SC_RSTCTRL7_UMC30 (1 << 0) 30 31 #define SC_CLKCTRL (SC_BASE_ADDR | 0x2100) 32 #define SC_CLKCTRL3 (SC_BASE_ADDR | 0x2108) 33 #define SC_CLKCTRL4 (SC_BASE_ADDR | 0x210c) 34 #define SC_CLKCTRL4_MIO (1 << 10) 35 #define SC_CLKCTRL4_STDMAC (1 << 8) 36 #define SC_CLKCTRL4_PERI (1 << 7) 37 #define SC_CLKCTRL4_ETHER (1 << 6) 38 #define SC_CLKCTRL4_NAND (1 << 0) 39 #define SC_CLKCTRL5 (SC_BASE_ADDR | 0x2110) 40 #define SC_CLKCTRL6 (SC_BASE_ADDR | 0x2114) 41 #define SC_CLKCTRL7 (SC_BASE_ADDR | 0x2118) 42 #define SC_CLKCTRL7_UMCSB (1 << 16) 43 #define SC_CLKCTRL7_UMC32 (1 << 2) 44 #define SC_CLKCTRL7_UMC31 (1 << 1) 45 #define SC_CLKCTRL7_UMC30 (1 << 0) 46 47 #define SC_CA72_GEARST (SC_BASE_ADDR | 0x8000) 48 #define SC_CA72_GEARSET (SC_BASE_ADDR | 0x8004) 49 #define SC_CA72_GEARUPD (SC_BASE_ADDR | 0x8008) 50 #define SC_CA53_GEARST (SC_BASE_ADDR | 0x8080) 51 #define SC_CA53_GEARSET (SC_BASE_ADDR | 0x8084) 52 #define SC_CA53_GEARUPD (SC_BASE_ADDR | 0x8088) 53 #define SC_CA_GEARUPD (1 << 0) 54 55 #endif /* SC64_REGS_H */ 56