1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * UniPhier SC (System Control) block registers
4  *
5  * Copyright (C) 2011-2015 Panasonic Corporation
6  * Copyright (C) 2015-2016 Socionext Inc.
7  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
8  */
9 
10 #ifndef ARCH_SC_REGS_H
11 #define ARCH_SC_REGS_H
12 
13 #define SC_BASE_ADDR			0x61840000
14 
15 #define SC_DPLLOSCCTRL			(SC_BASE_ADDR | 0x1110)
16 #define SC_DPLLOSCCTRL_DPLLST		(0x1 << 1)
17 #define SC_DPLLOSCCTRL_DPLLEN		(0x1 << 0)
18 
19 #define SC_DPLLCTRL			(SC_BASE_ADDR | 0x1200)
20 #define SC_DPLLCTRL_SSC_EN		(0x1 << 31)
21 #define SC_DPLLCTRL_FOUTMODE_MASK        (0xf << 16)
22 #define SC_DPLLCTRL_SSC_RATE		(0x1 << 15)
23 
24 #define SC_DPLLCTRL2			(SC_BASE_ADDR | 0x1204)
25 #define SC_DPLLCTRL2_NRSTDS		(0x1 << 28)
26 
27 #define SC_DPLLCTRL3			(SC_BASE_ADDR | 0x1208)
28 #define SC_DPLLCTRL3_LPFSEL_COEF2	(0x0 << 31)
29 #define SC_DPLLCTRL3_LPFSEL_COEF3	(0x1 << 31)
30 
31 #define SC_UPLLCTRL			(SC_BASE_ADDR | 0x1210)
32 
33 #define SC_VPLL27ACTRL			(SC_BASE_ADDR | 0x1270)
34 #define SC_VPLL27ACTRL2			(SC_BASE_ADDR | 0x1274)
35 #define SC_VPLL27ACTRL3			(SC_BASE_ADDR | 0x1278)
36 
37 #define SC_VPLL27BCTRL			(SC_BASE_ADDR | 0x1290)
38 #define SC_VPLL27BCTRL2			(SC_BASE_ADDR | 0x1294)
39 #define SC_VPLL27BCTRL3			(SC_BASE_ADDR | 0x1298)
40 
41 #define SC_RSTCTRL			(SC_BASE_ADDR | 0x2000)
42 #define SC_RSTCTRL_NRST_USB3B0		(0x1 << 17)	/* USB3 #0 bus */
43 #define SC_RSTCTRL_NRST_USB3C0		(0x1 << 16)	/* USB3 #0 core */
44 #define SC_RSTCTRL_NRST_ETHER		(0x1 << 12)
45 #define SC_RSTCTRL_NRST_STDMAC		(0x1 << 10)
46 #define SC_RSTCTRL_NRST_GIO		(0x1 <<  6)
47 /* Pro4 or older */
48 #define SC_RSTCTRL_NRST_UMC1		(0x1 <<  5)
49 #define SC_RSTCTRL_NRST_UMC0		(0x1 <<  4)
50 #define SC_RSTCTRL_NRST_NAND		(0x1 <<  2)
51 
52 #define SC_RSTCTRL2			(SC_BASE_ADDR | 0x2004)
53 #define SC_RSTCTRL2_NRST_USB3B1		(0x1 << 17)	/* USB3 #1 bus */
54 #define SC_RSTCTRL2_NRST_USB3C1		(0x1 << 16)	/* USB3 #1 core */
55 
56 #define SC_RSTCTRL3			(SC_BASE_ADDR | 0x2008)
57 
58 /* Pro5 or newer */
59 #define SC_RSTCTRL4			(SC_BASE_ADDR | 0x200c)
60 #define SC_RSTCTRL4_NRST_UMCSB		(0x1 << 12)	/* UMC system bus */
61 #define SC_RSTCTRL4_NRST_UMCA2		(0x1 << 10)	/* UMC ch2 standby */
62 #define SC_RSTCTRL4_NRST_UMCA1		(0x1 <<  9)	/* UMC ch1 standby */
63 #define SC_RSTCTRL4_NRST_UMCA0		(0x1 <<  8)	/* UMC ch0 standby */
64 #define SC_RSTCTRL4_NRST_UMC32		(0x1 <<  6)	/* UMC ch2 */
65 #define SC_RSTCTRL4_NRST_UMC31		(0x1 <<  5)	/* UMC ch1 */
66 #define SC_RSTCTRL4_NRST_UMC30		(0x1 <<  4)	/* UMC ch0 */
67 
68 #define SC_RSTCTRL5			(SC_BASE_ADDR | 0x2010)
69 
70 #define SC_RSTCTRL6			(SC_BASE_ADDR | 0x2014)
71 
72 #define SC_CLKCTRL			(SC_BASE_ADDR | 0x2104)
73 #define SC_CLKCTRL_CEN_USB31		(0x1 << 17)	/* USB3 #1 */
74 #define SC_CLKCTRL_CEN_USB30		(0x1 << 16)	/* USB3 #0 */
75 #define SC_CLKCTRL_CEN_ETHER		(0x1 << 12)
76 #define SC_CLKCTRL_CEN_MIO		(0x1 << 11)
77 #define SC_CLKCTRL_CEN_STDMAC		(0x1 << 10)
78 #define SC_CLKCTRL_CEN_GIO		(0x1 <<  6)
79 /* Pro4 or older */
80 #define SC_CLKCTRL_CEN_UMC		(0x1 <<  4)
81 #define SC_CLKCTRL_CEN_NAND		(0x1 <<  2)
82 #define SC_CLKCTRL_CEN_SBC		(0x1 <<  1)
83 #define SC_CLKCTRL_CEN_PERI		(0x1 <<  0)
84 
85 /* Pro5 or newer */
86 #define SC_CLKCTRL4			(SC_BASE_ADDR | 0x210c)
87 #define SC_CLKCTRL4_CEN_UMCSB		(0x1 << 12)	/* UMC system bus */
88 #define SC_CLKCTRL4_CEN_UMC2		(0x1 <<  2)	/* UMC ch2 */
89 #define SC_CLKCTRL4_CEN_UMC1		(0x1 <<  1)	/* UMC ch1 */
90 #define SC_CLKCTRL4_CEN_UMC0		(0x1 <<  0)	/* UMC ch0 */
91 
92 /* System reset control register */
93 #define SC_IRQTIMSET			(SC_BASE_ADDR | 0x3000)
94 #define SC_SLFRSTSEL			(SC_BASE_ADDR | 0x3010)
95 #define SC_SLFRSTCTL			(SC_BASE_ADDR | 0x3014)
96 
97 #endif /* ARCH_SC_REGS_H */
98