1 /*
2  * UniPhier SC (System Control) block registers
3  *
4  * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #ifndef ARCH_SC_REGS_H
10 #define ARCH_SC_REGS_H
11 
12 #if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
13 #define SC_BASE_ADDR			0xf1840000
14 #else
15 #define SC_BASE_ADDR			0x61840000
16 #endif
17 
18 #define SC_DPLLOSCCTRL			(SC_BASE_ADDR | 0x1110)
19 #define SC_DPLLOSCCTRL_DPLLST		(0x1 << 1)
20 #define SC_DPLLOSCCTRL_DPLLEN		(0x1 << 0)
21 
22 #define SC_DPLLCTRL			(SC_BASE_ADDR | 0x1200)
23 #define SC_DPLLCTRL_SSC_EN		(0x1 << 31)
24 #define SC_DPLLCTRL_FOUTMODE_MASK        (0xf << 16)
25 #define SC_DPLLCTRL_SSC_RATE		(0x1 << 15)
26 
27 #define SC_DPLLCTRL2			(SC_BASE_ADDR | 0x1204)
28 #define SC_DPLLCTRL2_NRSTDS		(0x1 << 28)
29 
30 #define SC_DPLLCTRL3			(SC_BASE_ADDR | 0x1208)
31 #define SC_DPLLCTRL3_LPFSEL_COEF2	(0x0 << 31)
32 #define SC_DPLLCTRL3_LPFSEL_COEF3	(0x1 << 31)
33 
34 #define SC_UPLLCTRL			(SC_BASE_ADDR | 0x1210)
35 
36 #define SC_VPLL27ACTRL			(SC_BASE_ADDR | 0x1270)
37 #define SC_VPLL27ACTRL2			(SC_BASE_ADDR | 0x1274)
38 #define SC_VPLL27ACTRL3			(SC_BASE_ADDR | 0x1278)
39 
40 #define SC_VPLL27BCTRL			(SC_BASE_ADDR | 0x1290)
41 #define SC_VPLL27BCTRL2			(SC_BASE_ADDR | 0x1294)
42 #define SC_VPLL27BCTRL3			(SC_BASE_ADDR | 0x1298)
43 
44 #define SC_RSTCTRL			(SC_BASE_ADDR | 0x2000)
45 #define SC_RSTCTRL_NRST_USB3B0		(0x1 << 17)	/* USB3 #0 bus */
46 #define SC_RSTCTRL_NRST_USB3C0		(0x1 << 16)	/* USB3 #0 core */
47 #define SC_RSTCTRL_NRST_ETHER		(0x1 << 12)
48 #define SC_RSTCTRL_NRST_STDMAC		(0x1 << 10)
49 #define SC_RSTCTRL_NRST_GIO		(0x1 <<  6)
50 /* Pro4 or older */
51 #define SC_RSTCTRL_NRST_UMC1		(0x1 <<  5)
52 #define SC_RSTCTRL_NRST_UMC0		(0x1 <<  4)
53 #define SC_RSTCTRL_NRST_NAND		(0x1 <<  2)
54 
55 #define SC_RSTCTRL2			(SC_BASE_ADDR | 0x2004)
56 #define SC_RSTCTRL2_NRST_USB3B1		(0x1 << 17)	/* USB3 #1 bus */
57 #define SC_RSTCTRL2_NRST_USB3C1		(0x1 << 16)	/* USB3 #1 core */
58 
59 #define SC_RSTCTRL3			(SC_BASE_ADDR | 0x2008)
60 
61 /* Pro5 or newer */
62 #define SC_RSTCTRL4			(SC_BASE_ADDR | 0x200c)
63 #define SC_RSTCTRL4_NRST_UMCSB		(0x1 << 12)	/* UMC system bus */
64 #define SC_RSTCTRL4_NRST_UMCA2		(0x1 << 10)	/* UMC ch2 standby */
65 #define SC_RSTCTRL4_NRST_UMCA1		(0x1 <<  9)	/* UMC ch1 standby */
66 #define SC_RSTCTRL4_NRST_UMCA0		(0x1 <<  8)	/* UMC ch0 standby */
67 #define SC_RSTCTRL4_NRST_UMC32		(0x1 <<  6)	/* UMC ch2 */
68 #define SC_RSTCTRL4_NRST_UMC31		(0x1 <<  5)	/* UMC ch1 */
69 #define SC_RSTCTRL4_NRST_UMC30		(0x1 <<  4)	/* UMC ch0 */
70 
71 #define SC_CLKCTRL			(SC_BASE_ADDR | 0x2104)
72 #define SC_CLKCTRL_CEN_USB31		(0x1 << 17)	/* USB3 #1 */
73 #define SC_CLKCTRL_CEN_USB30		(0x1 << 16)	/* USB3 #0 */
74 #define SC_CLKCTRL_CEN_ETHER		(0x1 << 12)
75 #define SC_CLKCTRL_CEN_MIO		(0x1 << 11)
76 #define SC_CLKCTRL_CEN_STDMAC		(0x1 << 10)
77 #define SC_CLKCTRL_CEN_GIO		(0x1 <<  6)
78 /* Pro4 or older */
79 #define SC_CLKCTRL_CEN_UMC		(0x1 <<  4)
80 #define SC_CLKCTRL_CEN_NAND		(0x1 <<  2)
81 #define SC_CLKCTRL_CEN_SBC		(0x1 <<  1)
82 #define SC_CLKCTRL_CEN_PERI		(0x1 <<  0)
83 
84 /* Pro5 or newer */
85 #define SC_CLKCTRL4			(SC_BASE_ADDR | 0x210c)
86 #define SC_CLKCTRL4_CEN_UMCSB		(0x1 << 12)	/* UMC system bus */
87 #define SC_CLKCTRL4_CEN_UMC2		(0x1 <<  2)	/* UMC ch2 */
88 #define SC_CLKCTRL4_CEN_UMC1		(0x1 <<  1)	/* UMC ch1 */
89 #define SC_CLKCTRL4_CEN_UMC0		(0x1 <<  0)	/* UMC ch0 */
90 
91 /* System reset control register */
92 #define SC_IRQTIMSET			(SC_BASE_ADDR | 0x3000)
93 #define SC_SLFRSTSEL			(SC_BASE_ADDR | 0x3010)
94 #define SC_SLFRSTCTL			(SC_BASE_ADDR | 0x3014)
95 
96 #endif /* ARCH_SC_REGS_H */
97