1 /* 2 * Copyright (C) 2011-2015 Panasonic Corporation 3 * Copyright (C) 2015-2017 Socionext Inc. 4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <linux/io.h> 10 11 #include "../init.h" 12 #include "sbc-regs.h" 13 14 #define SBCTRL0_ADMULTIPLX_PERI_VALUE 0x33120000 15 #define SBCTRL1_ADMULTIPLX_PERI_VALUE 0x03005500 16 #define SBCTRL2_ADMULTIPLX_PERI_VALUE 0x14000020 17 18 #define SBCTRL0_ADMULTIPLX_MEM_VALUE 0x33120000 19 #define SBCTRL1_ADMULTIPLX_MEM_VALUE 0x03005500 20 #define SBCTRL2_ADMULTIPLX_MEM_VALUE 0x14000010 21 22 /* slower but LED works */ 23 #define SBCTRL0_SAVEPIN_PERI_VALUE 0x55450000 24 #define SBCTRL1_SAVEPIN_PERI_VALUE 0x07168d00 25 #define SBCTRL2_SAVEPIN_PERI_VALUE 0x34000009 26 #define SBCTRL4_SAVEPIN_PERI_VALUE 0x02110110 27 28 /* faster but LED does not work */ 29 #define SBCTRL0_SAVEPIN_MEM_VALUE 0x55450000 30 #define SBCTRL1_SAVEPIN_MEM_VALUE 0x06057700 31 /* NOR flash needs more wait counts than SRAM */ 32 #define SBCTRL2_SAVEPIN_MEM_VALUE 0x34000009 33 #define SBCTRL4_SAVEPIN_MEM_VALUE 0x02110210 34 35 static void __uniphier_sbc_init(int savepin) 36 { 37 /* 38 * Only CS1 is connected to support card. 39 * BKSZ[1:0] should be set to "01". 40 */ 41 if (savepin) { 42 writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10); 43 writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11); 44 writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12); 45 writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14); 46 } else { 47 writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL10); 48 writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL11); 49 writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL12); 50 } 51 52 if (boot_is_swapped()) { 53 /* 54 * Boot Swap On: boot from external NOR/SRAM 55 * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff. 56 * 57 * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank 58 * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals 59 */ 60 writel(0x0000bc01, SBBASE0); 61 } else { 62 /* 63 * Boot Swap Off: boot from mask ROM 64 * 0x40000000-0x41ffffff: mask ROM 65 * 0x42000000-0x43efffff: memory bank (31MB) 66 * 0x43f00000-0x43ffffff: peripherals (1MB) 67 */ 68 writel(0x0000be01, SBBASE0); /* dummy */ 69 writel(0x0200be01, SBBASE1); 70 } 71 } 72 73 void uniphier_sbc_init_admulti(void) 74 { 75 __uniphier_sbc_init(0); 76 } 77 78 void uniphier_sbc_init_savepin(void) 79 { 80 __uniphier_sbc_init(1); 81 } 82