1 /*
2  * UniPhier SBC (System Bus Controller) registers
3  *
4  * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #ifndef ARCH_SBC_REGS_H
10 #define ARCH_SBC_REGS_H
11 
12 #define	SBBASE_BASE		0x58c00100
13 #define	SBBASE(x)		(SBBASE_BASE + (x) * 0x10)
14 
15 #define	SBBASE0			(SBBASE(0))
16 #define	SBBASE1			(SBBASE(1))
17 #define	SBBASE2			(SBBASE(2))
18 #define	SBBASE3			(SBBASE(3))
19 #define	SBBASE4			(SBBASE(4))
20 #define	SBBASE5			(SBBASE(5))
21 #define	SBBASE6			(SBBASE(6))
22 #define	SBBASE7			(SBBASE(7))
23 
24 #define	SBBASE_BANK_ENABLE	(0x00000001)
25 
26 #define	SBCTRL_BASE		0x58c00200
27 #define	SBCTRL(x, y)		(SBCTRL_BASE + (x) * 0x10 + (y) * 4)
28 
29 #define	SBCTRL00		SBCTRL(0, 0)
30 #define	SBCTRL01		SBCTRL(0, 1)
31 #define	SBCTRL02		SBCTRL(0, 2)
32 #define	SBCTRL03		SBCTRL(0, 3)
33 #define	SBCTRL04		(SBCTRL_BASE + 0x100)
34 
35 #define	SBCTRL10		SBCTRL(1, 0)
36 #define	SBCTRL11		SBCTRL(1, 1)
37 #define	SBCTRL12		SBCTRL(1, 2)
38 #define	SBCTRL13		SBCTRL(1, 3)
39 #define	SBCTRL14		(SBCTRL_BASE + 0x110)
40 
41 #define	SBCTRL20		SBCTRL(2, 0)
42 #define	SBCTRL21		SBCTRL(2, 1)
43 #define	SBCTRL22		SBCTRL(2, 2)
44 #define	SBCTRL23		SBCTRL(2, 3)
45 #define	SBCTRL24		(SBCTRL_BASE + 0x120)
46 
47 #define	SBCTRL30		SBCTRL(3, 0)
48 #define	SBCTRL31		SBCTRL(3, 1)
49 #define	SBCTRL32		SBCTRL(3, 2)
50 #define	SBCTRL33		SBCTRL(3, 3)
51 #define	SBCTRL34		(SBCTRL_BASE + 0x130)
52 
53 #define	SBCTRL40		SBCTRL(4, 0)
54 #define	SBCTRL41		SBCTRL(4, 1)
55 #define	SBCTRL42		SBCTRL(4, 2)
56 #define	SBCTRL43		SBCTRL(4, 3)
57 #define	SBCTRL44		(SBCTRL_BASE + 0x140)
58 
59 #define	SBCTRL50		SBCTRL(5, 0)
60 #define	SBCTRL51		SBCTRL(5, 1)
61 #define	SBCTRL52		SBCTRL(5, 2)
62 #define	SBCTRL53		SBCTRL(5, 3)
63 #define	SBCTRL54		(SBCTRL_BASE + 0x150)
64 
65 #define	SBCTRL60		SBCTRL(6, 0)
66 #define	SBCTRL61		SBCTRL(6, 1)
67 #define	SBCTRL62		SBCTRL(6, 2)
68 #define	SBCTRL63		SBCTRL(6, 3)
69 #define	SBCTRL64		(SBCTRL_BASE + 0x160)
70 
71 #define	SBCTRL70		SBCTRL(7, 0)
72 #define	SBCTRL71		SBCTRL(7, 1)
73 #define	SBCTRL72		SBCTRL(7, 2)
74 #define	SBCTRL73		SBCTRL(7, 3)
75 #define	SBCTRL74		(SBCTRL_BASE + 0x170)
76 
77 /* slower but LED works */
78 #define SBCTRL0_SAVEPIN_PERI_VALUE	0x55450000
79 #define SBCTRL1_SAVEPIN_PERI_VALUE	0x07168d00
80 #define SBCTRL2_SAVEPIN_PERI_VALUE	0x34000009
81 #define SBCTRL4_SAVEPIN_PERI_VALUE	0x02110110
82 
83 /* faster but LED does not work */
84 #define SBCTRL0_SAVEPIN_MEM_VALUE	0x55450000
85 #define SBCTRL1_SAVEPIN_MEM_VALUE	0x06057700
86 /* NOR flash needs more wait counts than SRAM */
87 #define SBCTRL2_SAVEPIN_MEM_VALUE	0x34000009
88 #define SBCTRL4_SAVEPIN_MEM_VALUE	0x02110210
89 
90 #define SBCTRL0_ADMULTIPLX_PERI_VALUE	0x33120000
91 #define SBCTRL1_ADMULTIPLX_PERI_VALUE	0x03005500
92 #define SBCTRL2_ADMULTIPLX_PERI_VALUE	0x14000020
93 
94 #define SBCTRL0_ADMULTIPLX_MEM_VALUE	0x33120000
95 #define SBCTRL1_ADMULTIPLX_MEM_VALUE	0x03005500
96 #define SBCTRL2_ADMULTIPLX_MEM_VALUE	0x14000010
97 
98 #define PC0CTRL				0x598000c0
99 #define ROM_BOOT_ROMRSV2		0x59801208
100 
101 #ifndef __ASSEMBLY__
102 #include <linux/io.h>
103 static inline int boot_is_swapped(void)
104 {
105 	return !(readl(SBBASE0) & SBBASE_BANK_ENABLE);
106 }
107 #endif
108 
109 #endif	/* ARCH_SBC_REGS_H */
110