1 /* 2 * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <linux/err.h> 9 #include <linux/io.h> 10 #include <linux/sizes.h> 11 #include <asm/processor.h> 12 13 #include "../init.h" 14 #include "ddrphy-regs.h" 15 #include "umc-regs.h" 16 17 #define DRAM_CH_NR 2 18 19 enum dram_freq { 20 DRAM_FREQ_1333M, 21 DRAM_FREQ_1600M, 22 DRAM_FREQ_NR, 23 }; 24 25 enum dram_size { 26 DRAM_SZ_128M, 27 DRAM_SZ_256M, 28 DRAM_SZ_512M, 29 DRAM_SZ_NR, 30 }; 31 32 static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x55990b11, 0x66bb0f17}; 33 static u32 umc_cmdctla_plus[DRAM_FREQ_NR] = {0x45990b11, 0x46bb0f17}; 34 static u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x16958944, 0x18c6ab44}; 35 static u32 umc_cmdctlb_plus[DRAM_FREQ_NR] = {0x16958924, 0x18c6ab24}; 36 static u32 umc_spcctla[DRAM_FREQ_NR][DRAM_SZ_NR] = { 37 {0x00240512, 0x00350512, 0x00000000}, /* no data for 1333MHz,128MB */ 38 {0x002b0617, 0x003f0617, 0x00670617}, 39 }; 40 static u32 umc_spcctlb[DRAM_FREQ_NR] = {0x00ff0006, 0x00ff0008}; 41 static u32 umc_rdatactl[DRAM_FREQ_NR] = {0x000a00ac, 0x000c00ac}; 42 43 static int umc_get_rank(int ch) 44 { 45 return ch; /* ch0: rank0, ch1: rank1 for this SoC */ 46 } 47 48 static void umc_start_ssif(void __iomem *ssif_base) 49 { 50 writel(0x00000000, ssif_base + 0x0000b004); 51 writel(0xffffffff, ssif_base + 0x0000c004); 52 writel(0x000fffcf, ssif_base + 0x0000c008); 53 writel(0x00000001, ssif_base + 0x0000b000); 54 writel(0x00000001, ssif_base + 0x0000c000); 55 writel(0x03010101, ssif_base + UMC_MDMCHSEL); 56 writel(0x03010100, ssif_base + UMC_DMDCHSEL); 57 58 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH); 59 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0); 60 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0); 61 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0); 62 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1); 63 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1); 64 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1); 65 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC); 66 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC); 67 writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST); 68 69 writel(0x00000001, ssif_base + UMC_CPURST); 70 writel(0x00000001, ssif_base + UMC_IDSRST); 71 writel(0x00000001, ssif_base + UMC_IXMRST); 72 writel(0x00000001, ssif_base + UMC_MDMRST); 73 writel(0x00000001, ssif_base + UMC_MDDRST); 74 writel(0x00000001, ssif_base + UMC_SIORST); 75 writel(0x00000001, ssif_base + UMC_VIORST); 76 writel(0x00000001, ssif_base + UMC_FRCRST); 77 writel(0x00000001, ssif_base + UMC_RGLRST); 78 writel(0x00000001, ssif_base + UMC_AIORST); 79 writel(0x00000001, ssif_base + UMC_DMDRST); 80 } 81 82 static int umc_dramcont_init(void __iomem *dc_base, void __iomem *ca_base, 83 int freq, unsigned long size, bool ddr3plus) 84 { 85 enum dram_freq freq_e; 86 enum dram_size size_e; 87 88 switch (freq) { 89 case 1333: 90 freq_e = DRAM_FREQ_1333M; 91 break; 92 case 1600: 93 freq_e = DRAM_FREQ_1600M; 94 break; 95 default: 96 pr_err("unsupported DRAM frequency %d MHz\n", freq); 97 return -EINVAL; 98 } 99 100 switch (size) { 101 case 0: 102 return 0; 103 case SZ_128M: 104 size_e = DRAM_SZ_128M; 105 break; 106 case SZ_256M: 107 size_e = DRAM_SZ_256M; 108 break; 109 case SZ_512M: 110 size_e = DRAM_SZ_512M; 111 break; 112 default: 113 pr_err("unsupported DRAM size 0x%08lx\n", size); 114 return -EINVAL; 115 } 116 117 writel((ddr3plus ? umc_cmdctla_plus : umc_cmdctla)[freq_e], 118 dc_base + UMC_CMDCTLA); 119 writel((ddr3plus ? umc_cmdctlb_plus : umc_cmdctlb)[freq_e], 120 dc_base + UMC_CMDCTLB); 121 writel(umc_spcctla[freq_e][size_e], dc_base + UMC_SPCCTLA); 122 writel(umc_spcctlb[freq_e], dc_base + UMC_SPCCTLB); 123 writel(umc_rdatactl[freq_e], dc_base + UMC_RDATACTL_D0); 124 writel(0x04060806, dc_base + UMC_WDATACTL_D0); 125 writel(0x04a02000, dc_base + UMC_DATASET); 126 writel(0x00000000, ca_base + 0x2300); 127 writel(0x00400020, dc_base + UMC_DCCGCTL); 128 writel(0x00000003, dc_base + 0x7000); 129 writel(0x0000004f, dc_base + 0x8000); 130 writel(0x000000c3, dc_base + 0x8004); 131 writel(0x00000077, dc_base + 0x8008); 132 writel(0x0000003b, dc_base + UMC_DICGCTLA); 133 writel(0x020a0808, dc_base + UMC_DICGCTLB); 134 writel(0x00000004, dc_base + UMC_FLOWCTLG); 135 writel(0x80000201, ca_base + 0xc20); 136 writel(0x0801e01e, dc_base + UMC_FLOWCTLA); 137 writel(0x00200000, dc_base + UMC_FLOWCTLB); 138 writel(0x00004444, dc_base + UMC_FLOWCTLC); 139 writel(0x200a0a00, dc_base + UMC_SPCSETB); 140 writel(0x00000000, dc_base + UMC_SPCSETD); 141 writel(0x00000520, dc_base + UMC_DFICUPDCTLA); 142 143 return 0; 144 } 145 146 static int umc_ch_init(void __iomem *dc_base, void __iomem *ca_base, 147 int freq, unsigned long size, bool ddr3plus, int ch) 148 { 149 void __iomem *phy_base = dc_base + 0x00001000; 150 int ret; 151 152 writel(UMC_INITSET_INIT1EN, dc_base + UMC_INITSET); 153 while (readl(dc_base + UMC_INITSET) & UMC_INITSTAT_INIT1ST) 154 cpu_relax(); 155 156 writel(0x00000101, dc_base + UMC_DIOCTLA); 157 158 ret = uniphier_ld4_ddrphy_init(phy_base, freq, ddr3plus); 159 if (ret) 160 return ret; 161 162 ddrphy_prepare_training(phy_base, umc_get_rank(ch)); 163 ret = ddrphy_training(phy_base); 164 if (ret) 165 return ret; 166 167 return umc_dramcont_init(dc_base, ca_base, freq, size, ddr3plus); 168 } 169 170 int uniphier_sld8_umc_init(const struct uniphier_board_data *bd) 171 { 172 void __iomem *umc_base = (void __iomem *)0x5b800000; 173 void __iomem *ca_base = umc_base + 0x00001000; 174 void __iomem *dc_base = umc_base + 0x00400000; 175 void __iomem *ssif_base = umc_base; 176 int ch, ret; 177 178 for (ch = 0; ch < DRAM_CH_NR; ch++) { 179 ret = umc_ch_init(dc_base, ca_base, bd->dram_freq, 180 bd->dram_ch[ch].size, 181 bd->dram_ddr3plus, ch); 182 if (ret) { 183 pr_err("failed to initialize UMC ch%d\n", ch); 184 return ret; 185 } 186 187 ca_base += 0x00001000; 188 dc_base += 0x00200000; 189 } 190 191 umc_start_ssif(ssif_base); 192 193 return 0; 194 } 195