1*ea65c980SMasahiro Yamada /* 2*ea65c980SMasahiro Yamada * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com> 3*ea65c980SMasahiro Yamada * 4*ea65c980SMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 5*ea65c980SMasahiro Yamada */ 6*ea65c980SMasahiro Yamada 7*ea65c980SMasahiro Yamada #include <common.h> 8*ea65c980SMasahiro Yamada #include <linux/err.h> 9*ea65c980SMasahiro Yamada #include <linux/io.h> 10*ea65c980SMasahiro Yamada #include <linux/sizes.h> 11*ea65c980SMasahiro Yamada #include <asm/processor.h> 12*ea65c980SMasahiro Yamada 13*ea65c980SMasahiro Yamada #include "../init.h" 14*ea65c980SMasahiro Yamada #include "ddrphy-regs.h" 15*ea65c980SMasahiro Yamada #include "umc-regs.h" 16*ea65c980SMasahiro Yamada 17*ea65c980SMasahiro Yamada #define DRAM_CH_NR 2 18*ea65c980SMasahiro Yamada 19*ea65c980SMasahiro Yamada enum dram_freq { 20*ea65c980SMasahiro Yamada DRAM_FREQ_1333M, 21*ea65c980SMasahiro Yamada DRAM_FREQ_1600M, 22*ea65c980SMasahiro Yamada DRAM_FREQ_NR, 23*ea65c980SMasahiro Yamada }; 24*ea65c980SMasahiro Yamada 25*ea65c980SMasahiro Yamada enum dram_size { 26*ea65c980SMasahiro Yamada DRAM_SZ_128M, 27*ea65c980SMasahiro Yamada DRAM_SZ_256M, 28*ea65c980SMasahiro Yamada DRAM_SZ_512M, 29*ea65c980SMasahiro Yamada DRAM_SZ_NR, 30*ea65c980SMasahiro Yamada }; 31*ea65c980SMasahiro Yamada 32*ea65c980SMasahiro Yamada static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x55990b11, 0x66bb0f17}; 33*ea65c980SMasahiro Yamada static u32 umc_cmdctla_plus[DRAM_FREQ_NR] = {0x45990b11, 0x46bb0f17}; 34*ea65c980SMasahiro Yamada static u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x16958944, 0x18c6ab44}; 35*ea65c980SMasahiro Yamada static u32 umc_cmdctlb_plus[DRAM_FREQ_NR] = {0x16958924, 0x18c6ab24}; 36*ea65c980SMasahiro Yamada static u32 umc_spcctla[DRAM_FREQ_NR][DRAM_SZ_NR] = { 37*ea65c980SMasahiro Yamada {0x00240512, 0x00350512, 0x00000000}, /* no data for 1333MHz,128MB */ 38*ea65c980SMasahiro Yamada {0x002b0617, 0x003f0617, 0x00670617}, 39*ea65c980SMasahiro Yamada }; 40*ea65c980SMasahiro Yamada static u32 umc_spcctlb[DRAM_FREQ_NR] = {0x00ff0006, 0x00ff0008}; 41*ea65c980SMasahiro Yamada static u32 umc_rdatactl[DRAM_FREQ_NR] = {0x000a00ac, 0x000c00ac}; 42*ea65c980SMasahiro Yamada 43*ea65c980SMasahiro Yamada static int umc_get_rank(int ch) 44*ea65c980SMasahiro Yamada { 45*ea65c980SMasahiro Yamada return ch; /* ch0: rank0, ch1: rank1 for this SoC */ 46*ea65c980SMasahiro Yamada } 47*ea65c980SMasahiro Yamada 48*ea65c980SMasahiro Yamada static void umc_start_ssif(void __iomem *ssif_base) 49*ea65c980SMasahiro Yamada { 50*ea65c980SMasahiro Yamada writel(0x00000000, ssif_base + 0x0000b004); 51*ea65c980SMasahiro Yamada writel(0xffffffff, ssif_base + 0x0000c004); 52*ea65c980SMasahiro Yamada writel(0x000fffcf, ssif_base + 0x0000c008); 53*ea65c980SMasahiro Yamada writel(0x00000001, ssif_base + 0x0000b000); 54*ea65c980SMasahiro Yamada writel(0x00000001, ssif_base + 0x0000c000); 55*ea65c980SMasahiro Yamada writel(0x03010101, ssif_base + UMC_MDMCHSEL); 56*ea65c980SMasahiro Yamada writel(0x03010100, ssif_base + UMC_DMDCHSEL); 57*ea65c980SMasahiro Yamada 58*ea65c980SMasahiro Yamada writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH); 59*ea65c980SMasahiro Yamada writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0); 60*ea65c980SMasahiro Yamada writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0); 61*ea65c980SMasahiro Yamada writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0); 62*ea65c980SMasahiro Yamada writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1); 63*ea65c980SMasahiro Yamada writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1); 64*ea65c980SMasahiro Yamada writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1); 65*ea65c980SMasahiro Yamada writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC); 66*ea65c980SMasahiro Yamada writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC); 67*ea65c980SMasahiro Yamada writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST); 68*ea65c980SMasahiro Yamada 69*ea65c980SMasahiro Yamada writel(0x00000001, ssif_base + UMC_CPURST); 70*ea65c980SMasahiro Yamada writel(0x00000001, ssif_base + UMC_IDSRST); 71*ea65c980SMasahiro Yamada writel(0x00000001, ssif_base + UMC_IXMRST); 72*ea65c980SMasahiro Yamada writel(0x00000001, ssif_base + UMC_MDMRST); 73*ea65c980SMasahiro Yamada writel(0x00000001, ssif_base + UMC_MDDRST); 74*ea65c980SMasahiro Yamada writel(0x00000001, ssif_base + UMC_SIORST); 75*ea65c980SMasahiro Yamada writel(0x00000001, ssif_base + UMC_VIORST); 76*ea65c980SMasahiro Yamada writel(0x00000001, ssif_base + UMC_FRCRST); 77*ea65c980SMasahiro Yamada writel(0x00000001, ssif_base + UMC_RGLRST); 78*ea65c980SMasahiro Yamada writel(0x00000001, ssif_base + UMC_AIORST); 79*ea65c980SMasahiro Yamada writel(0x00000001, ssif_base + UMC_DMDRST); 80*ea65c980SMasahiro Yamada } 81*ea65c980SMasahiro Yamada 82*ea65c980SMasahiro Yamada static int umc_dramcont_init(void __iomem *dc_base, void __iomem *ca_base, 83*ea65c980SMasahiro Yamada int freq, unsigned long size, bool ddr3plus) 84*ea65c980SMasahiro Yamada { 85*ea65c980SMasahiro Yamada enum dram_freq freq_e; 86*ea65c980SMasahiro Yamada enum dram_size size_e; 87*ea65c980SMasahiro Yamada 88*ea65c980SMasahiro Yamada switch (freq) { 89*ea65c980SMasahiro Yamada case 1333: 90*ea65c980SMasahiro Yamada freq_e = DRAM_FREQ_1333M; 91*ea65c980SMasahiro Yamada break; 92*ea65c980SMasahiro Yamada case 1600: 93*ea65c980SMasahiro Yamada freq_e = DRAM_FREQ_1600M; 94*ea65c980SMasahiro Yamada break; 95*ea65c980SMasahiro Yamada default: 96*ea65c980SMasahiro Yamada pr_err("unsupported DRAM frequency %d MHz\n", freq); 97*ea65c980SMasahiro Yamada return -EINVAL; 98*ea65c980SMasahiro Yamada } 99*ea65c980SMasahiro Yamada 100*ea65c980SMasahiro Yamada switch (size) { 101*ea65c980SMasahiro Yamada case 0: 102*ea65c980SMasahiro Yamada return 0; 103*ea65c980SMasahiro Yamada case SZ_128M: 104*ea65c980SMasahiro Yamada size_e = DRAM_SZ_128M; 105*ea65c980SMasahiro Yamada break; 106*ea65c980SMasahiro Yamada case SZ_256M: 107*ea65c980SMasahiro Yamada size_e = DRAM_SZ_256M; 108*ea65c980SMasahiro Yamada break; 109*ea65c980SMasahiro Yamada case SZ_512M: 110*ea65c980SMasahiro Yamada size_e = DRAM_SZ_512M; 111*ea65c980SMasahiro Yamada break; 112*ea65c980SMasahiro Yamada default: 113*ea65c980SMasahiro Yamada pr_err("unsupported DRAM size 0x%08lx\n", size); 114*ea65c980SMasahiro Yamada return -EINVAL; 115*ea65c980SMasahiro Yamada } 116*ea65c980SMasahiro Yamada 117*ea65c980SMasahiro Yamada writel((ddr3plus ? umc_cmdctla_plus : umc_cmdctla)[freq_e], 118*ea65c980SMasahiro Yamada dc_base + UMC_CMDCTLA); 119*ea65c980SMasahiro Yamada writel((ddr3plus ? umc_cmdctlb_plus : umc_cmdctlb)[freq_e], 120*ea65c980SMasahiro Yamada dc_base + UMC_CMDCTLB); 121*ea65c980SMasahiro Yamada writel(umc_spcctla[freq_e][size_e], dc_base + UMC_SPCCTLA); 122*ea65c980SMasahiro Yamada writel(umc_spcctlb[freq_e], dc_base + UMC_SPCCTLB); 123*ea65c980SMasahiro Yamada writel(umc_rdatactl[freq_e], dc_base + UMC_RDATACTL_D0); 124*ea65c980SMasahiro Yamada writel(0x04060806, dc_base + UMC_WDATACTL_D0); 125*ea65c980SMasahiro Yamada writel(0x04a02000, dc_base + UMC_DATASET); 126*ea65c980SMasahiro Yamada writel(0x00000000, ca_base + 0x2300); 127*ea65c980SMasahiro Yamada writel(0x00400020, dc_base + UMC_DCCGCTL); 128*ea65c980SMasahiro Yamada writel(0x00000003, dc_base + 0x7000); 129*ea65c980SMasahiro Yamada writel(0x0000004f, dc_base + 0x8000); 130*ea65c980SMasahiro Yamada writel(0x000000c3, dc_base + 0x8004); 131*ea65c980SMasahiro Yamada writel(0x00000077, dc_base + 0x8008); 132*ea65c980SMasahiro Yamada writel(0x0000003b, dc_base + UMC_DICGCTLA); 133*ea65c980SMasahiro Yamada writel(0x020a0808, dc_base + UMC_DICGCTLB); 134*ea65c980SMasahiro Yamada writel(0x00000004, dc_base + UMC_FLOWCTLG); 135*ea65c980SMasahiro Yamada writel(0x80000201, ca_base + 0xc20); 136*ea65c980SMasahiro Yamada writel(0x0801e01e, dc_base + UMC_FLOWCTLA); 137*ea65c980SMasahiro Yamada writel(0x00200000, dc_base + UMC_FLOWCTLB); 138*ea65c980SMasahiro Yamada writel(0x00004444, dc_base + UMC_FLOWCTLC); 139*ea65c980SMasahiro Yamada writel(0x200a0a00, dc_base + UMC_SPCSETB); 140*ea65c980SMasahiro Yamada writel(0x00000000, dc_base + UMC_SPCSETD); 141*ea65c980SMasahiro Yamada writel(0x00000520, dc_base + UMC_DFICUPDCTLA); 142*ea65c980SMasahiro Yamada 143*ea65c980SMasahiro Yamada return 0; 144*ea65c980SMasahiro Yamada } 145*ea65c980SMasahiro Yamada 146*ea65c980SMasahiro Yamada static int umc_ch_init(void __iomem *dc_base, void __iomem *ca_base, 147*ea65c980SMasahiro Yamada int freq, unsigned long size, bool ddr3plus, int ch) 148*ea65c980SMasahiro Yamada { 149*ea65c980SMasahiro Yamada void __iomem *phy_base = dc_base + 0x00001000; 150*ea65c980SMasahiro Yamada int ret; 151*ea65c980SMasahiro Yamada 152*ea65c980SMasahiro Yamada writel(UMC_INITSET_INIT1EN, dc_base + UMC_INITSET); 153*ea65c980SMasahiro Yamada while (readl(dc_base + UMC_INITSET) & UMC_INITSTAT_INIT1ST) 154*ea65c980SMasahiro Yamada cpu_relax(); 155*ea65c980SMasahiro Yamada 156*ea65c980SMasahiro Yamada writel(0x00000101, dc_base + UMC_DIOCTLA); 157*ea65c980SMasahiro Yamada 158*ea65c980SMasahiro Yamada ret = ph1_ld4_ddrphy_init(phy_base, freq, ddr3plus); 159*ea65c980SMasahiro Yamada if (ret) 160*ea65c980SMasahiro Yamada return ret; 161*ea65c980SMasahiro Yamada 162*ea65c980SMasahiro Yamada ddrphy_prepare_training(phy_base, umc_get_rank(ch)); 163*ea65c980SMasahiro Yamada ret = ddrphy_training(phy_base); 164*ea65c980SMasahiro Yamada if (ret) 165*ea65c980SMasahiro Yamada return ret; 166*ea65c980SMasahiro Yamada 167*ea65c980SMasahiro Yamada return umc_dramcont_init(dc_base, ca_base, freq, size, ddr3plus); 168*ea65c980SMasahiro Yamada } 169*ea65c980SMasahiro Yamada 170*ea65c980SMasahiro Yamada int ph1_sld8_umc_init(const struct uniphier_board_data *bd) 171*ea65c980SMasahiro Yamada { 172*ea65c980SMasahiro Yamada void __iomem *umc_base = (void __iomem *)0x5b800000; 173*ea65c980SMasahiro Yamada void __iomem *ca_base = umc_base + 0x00001000; 174*ea65c980SMasahiro Yamada void __iomem *dc_base = umc_base + 0x00400000; 175*ea65c980SMasahiro Yamada void __iomem *ssif_base = umc_base; 176*ea65c980SMasahiro Yamada int ch, ret; 177*ea65c980SMasahiro Yamada 178*ea65c980SMasahiro Yamada for (ch = 0; ch < DRAM_CH_NR; ch++) { 179*ea65c980SMasahiro Yamada ret = umc_ch_init(dc_base, ca_base, bd->dram_freq, 180*ea65c980SMasahiro Yamada bd->dram_ch[ch].size, 181*ea65c980SMasahiro Yamada bd->dram_ddr3plus, ch); 182*ea65c980SMasahiro Yamada if (ret) { 183*ea65c980SMasahiro Yamada pr_err("failed to initialize UMC ch%d\n", ch); 184*ea65c980SMasahiro Yamada return ret; 185*ea65c980SMasahiro Yamada } 186*ea65c980SMasahiro Yamada 187*ea65c980SMasahiro Yamada ca_base += 0x00001000; 188*ea65c980SMasahiro Yamada dc_base += 0x00200000; 189*ea65c980SMasahiro Yamada } 190*ea65c980SMasahiro Yamada 191*ea65c980SMasahiro Yamada umc_start_ssif(ssif_base); 192*ea65c980SMasahiro Yamada 193*ea65c980SMasahiro Yamada return 0; 194*ea65c980SMasahiro Yamada } 195