1 /* 2 * UniPhier UMC (Universal Memory Controller) registers 3 * 4 * Copyright (C) 2011-2014 Panasonic Corporation 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef ARCH_UMC_REGS_H 10 #define ARCH_UMC_REGS_H 11 12 #define UMC_CPURST 0x00000700 13 #define UMC_IDSRST 0x0000070C 14 #define UMC_IXMRST 0x00000714 15 #define UMC_HDMRST 0x00000718 16 #define UMC_MDMRST 0x0000071C 17 #define UMC_HDDRST 0x00000720 18 #define UMC_MDDRST 0x00000724 19 #define UMC_SIORST 0x00000728 20 #define UMC_GIORST 0x0000072C 21 #define UMC_HD2RST 0x00000734 22 #define UMC_VIORST 0x0000073C 23 #define UMC_FRCRST 0x00000748 /* LD4/sLD8 */ 24 #define UMC_DVCRST 0x00000748 /* Pro4 */ 25 #define UMC_RGLRST 0x00000750 26 #define UMC_VPERST 0x00000758 27 #define UMC_AIORST 0x00000764 28 #define UMC_DMDRST 0x00000770 29 30 #define UMC_HDMCHSEL 0x00000898 31 #define UMC_MDMCHSEL 0x0000089C 32 #define UMC_DVCCHSEL 0x000008C8 33 #define UMC_DMDCHSEL 0x000008F0 34 35 #define UMC_CLKEN_SSIF_FETCH 0x0000C060 36 #define UMC_CLKEN_SSIF_COMQUE0 0x0000C064 37 #define UMC_CLKEN_SSIF_COMWC0 0x0000C068 38 #define UMC_CLKEN_SSIF_COMRC0 0x0000C06C 39 #define UMC_CLKEN_SSIF_COMQUE1 0x0000C070 40 #define UMC_CLKEN_SSIF_COMWC1 0x0000C074 41 #define UMC_CLKEN_SSIF_COMRC1 0x0000C078 42 #define UMC_CLKEN_SSIF_WC 0x0000C07C 43 #define UMC_CLKEN_SSIF_RC 0x0000C080 44 #define UMC_CLKEN_SSIF_DST 0x0000C084 45 46 #define UMC_CMDCTLA 0x00000000 47 #define UMC_CMDCTLB 0x00000004 48 #define UMC_INITSET 0x00000014 49 #define UMC_INITSTAT 0x00000018 50 #define UMC_SPCCTLA 0x00000030 51 #define UMC_SPCCTLB 0x00000034 52 #define UMC_SPCSETA 0x00000038 53 #define UMC_SPCSETB 0x0000003C 54 #define UMC_SPCSETB_AREFMD_MASK (0x3) /* Auto Refresh Mode */ 55 #define UMC_SPCSETB_AREFMD_ARB (0x0) /* control by arbitor */ 56 #define UMC_SPCSETB_AREFMD_CONT (0x1) /* control by DRAMCONT */ 57 #define UMC_SPCSETB_AREFMD_REG (0x2) /* control by register */ 58 #define UMC_SPCSETC 0x00000040 59 #define UMC_SPCSETD 0x00000044 60 #define UMC_SPCSTATA 0x00000050 61 #define UMC_SPCSTATB 0x00000054 62 #define UMC_SPCSTATC 0x00000058 63 #define UMC_ACSSETA 0x00000060 64 #define UMC_FLOWCTLA 0x00000400 65 #define UMC_FLOWCTLB 0x00000404 66 #define UMC_FLOWCTLC 0x00000408 67 #define UMC_FLOWCTLG 0x00000508 68 #define UMC_FLOWCTLOB0 0x00000520 69 #define UMC_FLOWCTLOB1 0x00000524 70 #define UMC_RDATACTL_D0 0x00000600 71 #define UMC_RDATACTL_RADLTY_SHIFT 4 72 #define UMC_RDATACTL_RADLTY_MASK (0xf << (UMC_RDATACTL_RADLTY_SHIFT)) 73 #define UMC_RDATACTL_RAD2LTY_SHIFT 8 74 #define UMC_RDATACTL_RAD2LTY_MASK (0xf << (UMC_RDATACTL_RAD2LTY_SHIFT)) 75 #define UMC_WDATACTL_D0 0x00000604 76 #define UMC_RDATACTL_D1 0x00000608 77 #define UMC_WDATACTL_D1 0x0000060C 78 #define UMC_DATASET 0x00000610 79 #define UMC_RESPCTL 0x00000624 80 #define UMC_DCCGCTL 0x00000720 81 #define UMC_DICGCTLA 0x00000724 82 #define UMC_DICGCTLB 0x00000728 83 #define UMC_ERRMASKA 0x00000958 84 #define UMC_ERRMASKB 0x0000095c 85 #define UMC_BSICMAPSET 0x00000988 86 #define UMC_DIOCTLA 0x00000C00 87 #define UMC_DIOCTLA_CTL_NRST BIT(8) /* ctl_rst_n */ 88 #define UMC_DIOCTLA_CFG_NRST BIT(0) /* cfg_rst_n */ 89 #define UMC_DFICUPDCTLA 0x00000C20 90 91 /* UM registers */ 92 #define UMC_MBUS0 0x00080004 93 #define UMC_MBUS1 0x00081004 94 #define UMC_MBUS2 0x00082004 95 #define UMC_MBUS3 0x00083004 96 97 /* UD registers */ 98 #define UMC_BITPERPIXELMODE_D0 0x010 99 #define UMC_PAIR1DOFF_D0 0x054 100 101 #ifndef __ASSEMBLY__ 102 103 #include <linux/types.h> 104 105 static inline void umc_dram_init_start(void __iomem *dramcont) 106 { 107 writel(0x00000002, dramcont + UMC_INITSET); 108 } 109 110 static inline void umc_dram_init_poll(void __iomem *dramcont) 111 { 112 while ((readl(dramcont + UMC_INITSTAT) & 0x00000002)) 113 ; 114 } 115 116 #endif 117 118 #endif 119