1107b3fb4SMasahiro Yamada /* 2107b3fb4SMasahiro Yamada * UniPhier UMC (Universal Memory Controller) registers 3107b3fb4SMasahiro Yamada * 4107b3fb4SMasahiro Yamada * Copyright (C) 2011-2014 Panasonic Corporation 5107b3fb4SMasahiro Yamada * 6107b3fb4SMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 7107b3fb4SMasahiro Yamada */ 8107b3fb4SMasahiro Yamada 9107b3fb4SMasahiro Yamada #ifndef ARCH_UMC_REGS_H 10107b3fb4SMasahiro Yamada #define ARCH_UMC_REGS_H 11107b3fb4SMasahiro Yamada 12107b3fb4SMasahiro Yamada #define UMC_BASE 0x5b800000 13107b3fb4SMasahiro Yamada 14107b3fb4SMasahiro Yamada /* SSIF registers */ 15107b3fb4SMasahiro Yamada #define UMC_SSIF_BASE UMC_BASE 16107b3fb4SMasahiro Yamada 17107b3fb4SMasahiro Yamada #define UMC_CPURST 0x00000700 18107b3fb4SMasahiro Yamada #define UMC_IDSRST 0x0000070C 19107b3fb4SMasahiro Yamada #define UMC_IXMRST 0x00000714 20107b3fb4SMasahiro Yamada #define UMC_HDMRST 0x00000718 21107b3fb4SMasahiro Yamada #define UMC_MDMRST 0x0000071C 22107b3fb4SMasahiro Yamada #define UMC_HDDRST 0x00000720 23107b3fb4SMasahiro Yamada #define UMC_MDDRST 0x00000724 24107b3fb4SMasahiro Yamada #define UMC_SIORST 0x00000728 25107b3fb4SMasahiro Yamada #define UMC_GIORST 0x0000072C 26107b3fb4SMasahiro Yamada #define UMC_HD2RST 0x00000734 27107b3fb4SMasahiro Yamada #define UMC_VIORST 0x0000073C 28107b3fb4SMasahiro Yamada #define UMC_FRCRST 0x00000748 /* LD4/sLD8 */ 29107b3fb4SMasahiro Yamada #define UMC_DVCRST 0x00000748 /* Pro4 */ 30107b3fb4SMasahiro Yamada #define UMC_RGLRST 0x00000750 31107b3fb4SMasahiro Yamada #define UMC_VPERST 0x00000758 32107b3fb4SMasahiro Yamada #define UMC_AIORST 0x00000764 33107b3fb4SMasahiro Yamada #define UMC_DMDRST 0x00000770 34107b3fb4SMasahiro Yamada 35107b3fb4SMasahiro Yamada #define UMC_HDMCHSEL 0x00000898 36107b3fb4SMasahiro Yamada #define UMC_MDMCHSEL 0x0000089C 37107b3fb4SMasahiro Yamada #define UMC_DVCCHSEL 0x000008C8 38107b3fb4SMasahiro Yamada #define UMC_DMDCHSEL 0x000008F0 39107b3fb4SMasahiro Yamada 40107b3fb4SMasahiro Yamada #define UMC_CLKEN_SSIF_FETCH 0x0000C060 41107b3fb4SMasahiro Yamada #define UMC_CLKEN_SSIF_COMQUE0 0x0000C064 42107b3fb4SMasahiro Yamada #define UMC_CLKEN_SSIF_COMWC0 0x0000C068 43107b3fb4SMasahiro Yamada #define UMC_CLKEN_SSIF_COMRC0 0x0000C06C 44107b3fb4SMasahiro Yamada #define UMC_CLKEN_SSIF_COMQUE1 0x0000C070 45107b3fb4SMasahiro Yamada #define UMC_CLKEN_SSIF_COMWC1 0x0000C074 46107b3fb4SMasahiro Yamada #define UMC_CLKEN_SSIF_COMRC1 0x0000C078 47107b3fb4SMasahiro Yamada #define UMC_CLKEN_SSIF_WC 0x0000C07C 48107b3fb4SMasahiro Yamada #define UMC_CLKEN_SSIF_RC 0x0000C080 49107b3fb4SMasahiro Yamada #define UMC_CLKEN_SSIF_DST 0x0000C084 50107b3fb4SMasahiro Yamada 51107b3fb4SMasahiro Yamada /* CA registers */ 52107b3fb4SMasahiro Yamada #define UMC_CA_BASE(ch) (UMC_BASE + 0x00001000 + 0x00001000 * (ch)) 53107b3fb4SMasahiro Yamada 54107b3fb4SMasahiro Yamada /* DRAM controller registers */ 55107b3fb4SMasahiro Yamada #define UMC_DRAMCONT_BASE(ch) (UMC_BASE + 0x00400000 + 0x00200000 * (ch)) 56107b3fb4SMasahiro Yamada 57107b3fb4SMasahiro Yamada #define UMC_CMDCTLA 0x00000000 58107b3fb4SMasahiro Yamada #define UMC_CMDCTLB 0x00000004 59107b3fb4SMasahiro Yamada #define UMC_INITCTLA 0x00000008 60107b3fb4SMasahiro Yamada #define UMC_INITCTLB 0x0000000C 61107b3fb4SMasahiro Yamada #define UMC_INITCTLC 0x00000010 62107b3fb4SMasahiro Yamada #define UMC_INITSET 0x00000014 63107b3fb4SMasahiro Yamada #define UMC_INITSTAT 0x00000018 64107b3fb4SMasahiro Yamada #define UMC_DRMMR0 0x0000001C 65107b3fb4SMasahiro Yamada #define UMC_DRMMR1 0x00000020 66107b3fb4SMasahiro Yamada #define UMC_DRMMR2 0x00000024 67107b3fb4SMasahiro Yamada #define UMC_DRMMR3 0x00000028 68107b3fb4SMasahiro Yamada #define UMC_SPCCTLA 0x00000030 69107b3fb4SMasahiro Yamada #define UMC_SPCCTLB 0x00000034 70107b3fb4SMasahiro Yamada #define UMC_SPCSETA 0x00000038 71107b3fb4SMasahiro Yamada #define UMC_SPCSETB 0x0000003C 72*faefef99SMasahiro Yamada #define UMC_SPCSETB_AREFMD_MASK (0x3) /* Auto Refresh Mode */ 73*faefef99SMasahiro Yamada #define UMC_SPCSETB_AREFMD_ARB (0x0) /* control by arbitor */ 74*faefef99SMasahiro Yamada #define UMC_SPCSETB_AREFMD_CONT (0x1) /* control by DRAMCONT */ 75*faefef99SMasahiro Yamada #define UMC_SPCSETB_AREFMD_REG (0x2) /* control by register */ 76107b3fb4SMasahiro Yamada #define UMC_SPCSETC 0x00000040 77107b3fb4SMasahiro Yamada #define UMC_SPCSETD 0x00000044 78107b3fb4SMasahiro Yamada #define UMC_SPCSTATA 0x00000050 79107b3fb4SMasahiro Yamada #define UMC_SPCSTATB 0x00000054 80107b3fb4SMasahiro Yamada #define UMC_SPCSTATC 0x00000058 81107b3fb4SMasahiro Yamada #define UMC_ACSSETA 0x00000060 82107b3fb4SMasahiro Yamada #define UMC_FLOWCTLA 0x00000400 83107b3fb4SMasahiro Yamada #define UMC_FLOWCTLB 0x00000404 84107b3fb4SMasahiro Yamada #define UMC_FLOWCTLC 0x00000408 85107b3fb4SMasahiro Yamada #define UMC_FLOWCTLG 0x00000508 86*faefef99SMasahiro Yamada #define UMC_FLOWCTLOB0 0x00000520 87*faefef99SMasahiro Yamada #define UMC_FLOWCTLOB1 0x00000524 88107b3fb4SMasahiro Yamada #define UMC_RDATACTL_D0 0x00000600 89*faefef99SMasahiro Yamada #define UMC_RDATACTL_RADLTY_SHIFT 4 90*faefef99SMasahiro Yamada #define UMC_RDATACTL_RADLTY_MASK (0xf << (UMC_RDATACTL_RADLTY_SHIFT)) 91*faefef99SMasahiro Yamada #define UMC_RDATACTL_RAD2LTY_SHIFT 8 92*faefef99SMasahiro Yamada #define UMC_RDATACTL_RAD2LTY_MASK (0xf << (UMC_RDATACTL_RAD2LTY_SHIFT)) 93107b3fb4SMasahiro Yamada #define UMC_WDATACTL_D0 0x00000604 94107b3fb4SMasahiro Yamada #define UMC_RDATACTL_D1 0x00000608 95107b3fb4SMasahiro Yamada #define UMC_WDATACTL_D1 0x0000060C 96107b3fb4SMasahiro Yamada #define UMC_DATASET 0x00000610 97*faefef99SMasahiro Yamada #define UMC_RESPCTL 0x00000624 98107b3fb4SMasahiro Yamada #define UMC_DCCGCTL 0x00000720 99107b3fb4SMasahiro Yamada #define UMC_DICGCTLA 0x00000724 100107b3fb4SMasahiro Yamada #define UMC_DICGCTLB 0x00000728 101*faefef99SMasahiro Yamada #define UMC_ERRMASKA 0x00000958 102*faefef99SMasahiro Yamada #define UMC_ERRMASKB 0x0000095c 103*faefef99SMasahiro Yamada #define UMC_BSICMAPSET 0x00000988 104107b3fb4SMasahiro Yamada #define UMC_DIOCTLA 0x00000C00 105*faefef99SMasahiro Yamada #define UMC_DIOCTLA_CTL_NRST BIT(8) /* ctl_rst_n */ 106*faefef99SMasahiro Yamada #define UMC_DIOCTLA_CFG_NRST BIT(0) /* cfg_rst_n */ 107107b3fb4SMasahiro Yamada #define UMC_DFICUPDCTLA 0x00000C20 108107b3fb4SMasahiro Yamada 109*faefef99SMasahiro Yamada /* UM registers */ 110*faefef99SMasahiro Yamada #define UMC_MBUS0 0x00080004 111*faefef99SMasahiro Yamada #define UMC_MBUS1 0x00081004 112*faefef99SMasahiro Yamada #define UMC_MBUS2 0x00082004 113*faefef99SMasahiro Yamada #define UMC_MBUS3 0x00083004 114*faefef99SMasahiro Yamada 115*faefef99SMasahiro Yamada /* UD registers */ 116*faefef99SMasahiro Yamada #define UMC_BITPERPIXELMODE_D0 0x010 117*faefef99SMasahiro Yamada #define UMC_PAIR1DOFF_D0 0x054 118*faefef99SMasahiro Yamada 119107b3fb4SMasahiro Yamada #ifndef __ASSEMBLY__ 120107b3fb4SMasahiro Yamada 121107b3fb4SMasahiro Yamada #include <linux/types.h> 122107b3fb4SMasahiro Yamada 123107b3fb4SMasahiro Yamada static inline void umc_polling(u32 address, u32 expval, u32 mask) 124107b3fb4SMasahiro Yamada { 125107b3fb4SMasahiro Yamada u32 nmask = ~mask; 126107b3fb4SMasahiro Yamada u32 data; 127107b3fb4SMasahiro Yamada do { 128107b3fb4SMasahiro Yamada data = readl(address) & nmask; 129107b3fb4SMasahiro Yamada } while (data != expval); 130107b3fb4SMasahiro Yamada } 131107b3fb4SMasahiro Yamada 132107b3fb4SMasahiro Yamada static inline void umc_dram_init_start(void __iomem *dramcont) 133107b3fb4SMasahiro Yamada { 134107b3fb4SMasahiro Yamada writel(0x00000002, dramcont + UMC_INITSET); 135107b3fb4SMasahiro Yamada } 136107b3fb4SMasahiro Yamada 137107b3fb4SMasahiro Yamada static inline void umc_dram_init_poll(void __iomem *dramcont) 138107b3fb4SMasahiro Yamada { 139107b3fb4SMasahiro Yamada while ((readl(dramcont + UMC_INITSTAT) & 0x00000002)) 140107b3fb4SMasahiro Yamada ; 141107b3fb4SMasahiro Yamada } 142107b3fb4SMasahiro Yamada 143107b3fb4SMasahiro Yamada #endif 144107b3fb4SMasahiro Yamada 145107b3fb4SMasahiro Yamada #endif 146