1107b3fb4SMasahiro Yamada /* 2107b3fb4SMasahiro Yamada * UniPhier UMC (Universal Memory Controller) registers 3107b3fb4SMasahiro Yamada * 4107b3fb4SMasahiro Yamada * Copyright (C) 2011-2014 Panasonic Corporation 5107b3fb4SMasahiro Yamada * 6107b3fb4SMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 7107b3fb4SMasahiro Yamada */ 8107b3fb4SMasahiro Yamada 9107b3fb4SMasahiro Yamada #ifndef ARCH_UMC_REGS_H 10107b3fb4SMasahiro Yamada #define ARCH_UMC_REGS_H 11107b3fb4SMasahiro Yamada 12*a191e0deSMasahiro Yamada #include <linux/bitops.h> 13*a191e0deSMasahiro Yamada 14107b3fb4SMasahiro Yamada #define UMC_CPURST 0x00000700 15107b3fb4SMasahiro Yamada #define UMC_IDSRST 0x0000070C 16107b3fb4SMasahiro Yamada #define UMC_IXMRST 0x00000714 17107b3fb4SMasahiro Yamada #define UMC_HDMRST 0x00000718 18107b3fb4SMasahiro Yamada #define UMC_MDMRST 0x0000071C 19107b3fb4SMasahiro Yamada #define UMC_HDDRST 0x00000720 20107b3fb4SMasahiro Yamada #define UMC_MDDRST 0x00000724 21107b3fb4SMasahiro Yamada #define UMC_SIORST 0x00000728 22107b3fb4SMasahiro Yamada #define UMC_GIORST 0x0000072C 23107b3fb4SMasahiro Yamada #define UMC_HD2RST 0x00000734 24107b3fb4SMasahiro Yamada #define UMC_VIORST 0x0000073C 25107b3fb4SMasahiro Yamada #define UMC_FRCRST 0x00000748 /* LD4/sLD8 */ 26107b3fb4SMasahiro Yamada #define UMC_DVCRST 0x00000748 /* Pro4 */ 27107b3fb4SMasahiro Yamada #define UMC_RGLRST 0x00000750 28107b3fb4SMasahiro Yamada #define UMC_VPERST 0x00000758 29107b3fb4SMasahiro Yamada #define UMC_AIORST 0x00000764 30107b3fb4SMasahiro Yamada #define UMC_DMDRST 0x00000770 31107b3fb4SMasahiro Yamada 32107b3fb4SMasahiro Yamada #define UMC_HDMCHSEL 0x00000898 33107b3fb4SMasahiro Yamada #define UMC_MDMCHSEL 0x0000089C 34107b3fb4SMasahiro Yamada #define UMC_DVCCHSEL 0x000008C8 35107b3fb4SMasahiro Yamada #define UMC_DMDCHSEL 0x000008F0 36107b3fb4SMasahiro Yamada 37107b3fb4SMasahiro Yamada #define UMC_CLKEN_SSIF_FETCH 0x0000C060 38107b3fb4SMasahiro Yamada #define UMC_CLKEN_SSIF_COMQUE0 0x0000C064 39107b3fb4SMasahiro Yamada #define UMC_CLKEN_SSIF_COMWC0 0x0000C068 40107b3fb4SMasahiro Yamada #define UMC_CLKEN_SSIF_COMRC0 0x0000C06C 41107b3fb4SMasahiro Yamada #define UMC_CLKEN_SSIF_COMQUE1 0x0000C070 42107b3fb4SMasahiro Yamada #define UMC_CLKEN_SSIF_COMWC1 0x0000C074 43107b3fb4SMasahiro Yamada #define UMC_CLKEN_SSIF_COMRC1 0x0000C078 44107b3fb4SMasahiro Yamada #define UMC_CLKEN_SSIF_WC 0x0000C07C 45107b3fb4SMasahiro Yamada #define UMC_CLKEN_SSIF_RC 0x0000C080 46107b3fb4SMasahiro Yamada #define UMC_CLKEN_SSIF_DST 0x0000C084 47107b3fb4SMasahiro Yamada 48107b3fb4SMasahiro Yamada #define UMC_CMDCTLA 0x00000000 49107b3fb4SMasahiro Yamada #define UMC_CMDCTLB 0x00000004 50107b3fb4SMasahiro Yamada #define UMC_INITSET 0x00000014 51*a191e0deSMasahiro Yamada #define UMC_INITSET_INIT1EN BIT(1) /* init without power-on wait */ 52*a191e0deSMasahiro Yamada #define UMC_INITSET_INIT0EN BIT(0) /* init with power-on wait */ 53107b3fb4SMasahiro Yamada #define UMC_INITSTAT 0x00000018 54*a191e0deSMasahiro Yamada #define UMC_INITSTAT_INIT1ST BIT(1) /* init without power-on wait */ 55*a191e0deSMasahiro Yamada #define UMC_INITSTAT_INIT0ST BIT(0) /* init with power-on wait */ 56107b3fb4SMasahiro Yamada #define UMC_SPCCTLA 0x00000030 57107b3fb4SMasahiro Yamada #define UMC_SPCCTLB 0x00000034 58107b3fb4SMasahiro Yamada #define UMC_SPCSETA 0x00000038 59107b3fb4SMasahiro Yamada #define UMC_SPCSETB 0x0000003C 60faefef99SMasahiro Yamada #define UMC_SPCSETB_AREFMD_MASK (0x3) /* Auto Refresh Mode */ 61faefef99SMasahiro Yamada #define UMC_SPCSETB_AREFMD_ARB (0x0) /* control by arbitor */ 62faefef99SMasahiro Yamada #define UMC_SPCSETB_AREFMD_CONT (0x1) /* control by DRAMCONT */ 63faefef99SMasahiro Yamada #define UMC_SPCSETB_AREFMD_REG (0x2) /* control by register */ 64107b3fb4SMasahiro Yamada #define UMC_SPCSETC 0x00000040 65107b3fb4SMasahiro Yamada #define UMC_SPCSETD 0x00000044 66107b3fb4SMasahiro Yamada #define UMC_SPCSTATA 0x00000050 67107b3fb4SMasahiro Yamada #define UMC_SPCSTATB 0x00000054 68107b3fb4SMasahiro Yamada #define UMC_SPCSTATC 0x00000058 69107b3fb4SMasahiro Yamada #define UMC_ACSSETA 0x00000060 70107b3fb4SMasahiro Yamada #define UMC_FLOWCTLA 0x00000400 71107b3fb4SMasahiro Yamada #define UMC_FLOWCTLB 0x00000404 72107b3fb4SMasahiro Yamada #define UMC_FLOWCTLC 0x00000408 73107b3fb4SMasahiro Yamada #define UMC_FLOWCTLG 0x00000508 74faefef99SMasahiro Yamada #define UMC_FLOWCTLOB0 0x00000520 75faefef99SMasahiro Yamada #define UMC_FLOWCTLOB1 0x00000524 76107b3fb4SMasahiro Yamada #define UMC_RDATACTL_D0 0x00000600 77faefef99SMasahiro Yamada #define UMC_RDATACTL_RADLTY_SHIFT 4 78faefef99SMasahiro Yamada #define UMC_RDATACTL_RADLTY_MASK (0xf << (UMC_RDATACTL_RADLTY_SHIFT)) 79faefef99SMasahiro Yamada #define UMC_RDATACTL_RAD2LTY_SHIFT 8 80faefef99SMasahiro Yamada #define UMC_RDATACTL_RAD2LTY_MASK (0xf << (UMC_RDATACTL_RAD2LTY_SHIFT)) 81107b3fb4SMasahiro Yamada #define UMC_WDATACTL_D0 0x00000604 82107b3fb4SMasahiro Yamada #define UMC_RDATACTL_D1 0x00000608 83107b3fb4SMasahiro Yamada #define UMC_WDATACTL_D1 0x0000060C 84107b3fb4SMasahiro Yamada #define UMC_DATASET 0x00000610 85faefef99SMasahiro Yamada #define UMC_RESPCTL 0x00000624 86107b3fb4SMasahiro Yamada #define UMC_DCCGCTL 0x00000720 87107b3fb4SMasahiro Yamada #define UMC_DICGCTLA 0x00000724 88107b3fb4SMasahiro Yamada #define UMC_DICGCTLB 0x00000728 89faefef99SMasahiro Yamada #define UMC_ERRMASKA 0x00000958 90faefef99SMasahiro Yamada #define UMC_ERRMASKB 0x0000095c 91faefef99SMasahiro Yamada #define UMC_BSICMAPSET 0x00000988 92107b3fb4SMasahiro Yamada #define UMC_DIOCTLA 0x00000C00 93faefef99SMasahiro Yamada #define UMC_DIOCTLA_CTL_NRST BIT(8) /* ctl_rst_n */ 94faefef99SMasahiro Yamada #define UMC_DIOCTLA_CFG_NRST BIT(0) /* cfg_rst_n */ 95107b3fb4SMasahiro Yamada #define UMC_DFICUPDCTLA 0x00000C20 96107b3fb4SMasahiro Yamada 97faefef99SMasahiro Yamada /* UM registers */ 98faefef99SMasahiro Yamada #define UMC_MBUS0 0x00080004 99faefef99SMasahiro Yamada #define UMC_MBUS1 0x00081004 100faefef99SMasahiro Yamada #define UMC_MBUS2 0x00082004 101faefef99SMasahiro Yamada #define UMC_MBUS3 0x00083004 102faefef99SMasahiro Yamada 103faefef99SMasahiro Yamada /* UD registers */ 104faefef99SMasahiro Yamada #define UMC_BITPERPIXELMODE_D0 0x010 105faefef99SMasahiro Yamada #define UMC_PAIR1DOFF_D0 0x054 106faefef99SMasahiro Yamada 107107b3fb4SMasahiro Yamada #endif 108