1*107b3fb4SMasahiro Yamada /* 2*107b3fb4SMasahiro Yamada * UniPhier UMC (Universal Memory Controller) registers 3*107b3fb4SMasahiro Yamada * 4*107b3fb4SMasahiro Yamada * Copyright (C) 2011-2014 Panasonic Corporation 5*107b3fb4SMasahiro Yamada * 6*107b3fb4SMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 7*107b3fb4SMasahiro Yamada */ 8*107b3fb4SMasahiro Yamada 9*107b3fb4SMasahiro Yamada #ifndef ARCH_UMC_REGS_H 10*107b3fb4SMasahiro Yamada #define ARCH_UMC_REGS_H 11*107b3fb4SMasahiro Yamada 12*107b3fb4SMasahiro Yamada #define UMC_BASE 0x5b800000 13*107b3fb4SMasahiro Yamada 14*107b3fb4SMasahiro Yamada /* SSIF registers */ 15*107b3fb4SMasahiro Yamada #define UMC_SSIF_BASE UMC_BASE 16*107b3fb4SMasahiro Yamada 17*107b3fb4SMasahiro Yamada #define UMC_CPURST 0x00000700 18*107b3fb4SMasahiro Yamada #define UMC_IDSRST 0x0000070C 19*107b3fb4SMasahiro Yamada #define UMC_IXMRST 0x00000714 20*107b3fb4SMasahiro Yamada #define UMC_HDMRST 0x00000718 21*107b3fb4SMasahiro Yamada #define UMC_MDMRST 0x0000071C 22*107b3fb4SMasahiro Yamada #define UMC_HDDRST 0x00000720 23*107b3fb4SMasahiro Yamada #define UMC_MDDRST 0x00000724 24*107b3fb4SMasahiro Yamada #define UMC_SIORST 0x00000728 25*107b3fb4SMasahiro Yamada #define UMC_GIORST 0x0000072C 26*107b3fb4SMasahiro Yamada #define UMC_HD2RST 0x00000734 27*107b3fb4SMasahiro Yamada #define UMC_VIORST 0x0000073C 28*107b3fb4SMasahiro Yamada #define UMC_FRCRST 0x00000748 /* LD4/sLD8 */ 29*107b3fb4SMasahiro Yamada #define UMC_DVCRST 0x00000748 /* Pro4 */ 30*107b3fb4SMasahiro Yamada #define UMC_RGLRST 0x00000750 31*107b3fb4SMasahiro Yamada #define UMC_VPERST 0x00000758 32*107b3fb4SMasahiro Yamada #define UMC_AIORST 0x00000764 33*107b3fb4SMasahiro Yamada #define UMC_DMDRST 0x00000770 34*107b3fb4SMasahiro Yamada 35*107b3fb4SMasahiro Yamada #define UMC_HDMCHSEL 0x00000898 36*107b3fb4SMasahiro Yamada #define UMC_MDMCHSEL 0x0000089C 37*107b3fb4SMasahiro Yamada #define UMC_DVCCHSEL 0x000008C8 38*107b3fb4SMasahiro Yamada #define UMC_DMDCHSEL 0x000008F0 39*107b3fb4SMasahiro Yamada 40*107b3fb4SMasahiro Yamada #define UMC_CLKEN_SSIF_FETCH 0x0000C060 41*107b3fb4SMasahiro Yamada #define UMC_CLKEN_SSIF_COMQUE0 0x0000C064 42*107b3fb4SMasahiro Yamada #define UMC_CLKEN_SSIF_COMWC0 0x0000C068 43*107b3fb4SMasahiro Yamada #define UMC_CLKEN_SSIF_COMRC0 0x0000C06C 44*107b3fb4SMasahiro Yamada #define UMC_CLKEN_SSIF_COMQUE1 0x0000C070 45*107b3fb4SMasahiro Yamada #define UMC_CLKEN_SSIF_COMWC1 0x0000C074 46*107b3fb4SMasahiro Yamada #define UMC_CLKEN_SSIF_COMRC1 0x0000C078 47*107b3fb4SMasahiro Yamada #define UMC_CLKEN_SSIF_WC 0x0000C07C 48*107b3fb4SMasahiro Yamada #define UMC_CLKEN_SSIF_RC 0x0000C080 49*107b3fb4SMasahiro Yamada #define UMC_CLKEN_SSIF_DST 0x0000C084 50*107b3fb4SMasahiro Yamada 51*107b3fb4SMasahiro Yamada /* CA registers */ 52*107b3fb4SMasahiro Yamada #define UMC_CA_BASE(ch) (UMC_BASE + 0x00001000 + 0x00001000 * (ch)) 53*107b3fb4SMasahiro Yamada 54*107b3fb4SMasahiro Yamada /* DRAM controller registers */ 55*107b3fb4SMasahiro Yamada #define UMC_DRAMCONT_BASE(ch) (UMC_BASE + 0x00400000 + 0x00200000 * (ch)) 56*107b3fb4SMasahiro Yamada 57*107b3fb4SMasahiro Yamada #define UMC_CMDCTLA 0x00000000 58*107b3fb4SMasahiro Yamada #define UMC_CMDCTLB 0x00000004 59*107b3fb4SMasahiro Yamada #define UMC_INITCTLA 0x00000008 60*107b3fb4SMasahiro Yamada #define UMC_INITCTLB 0x0000000C 61*107b3fb4SMasahiro Yamada #define UMC_INITCTLC 0x00000010 62*107b3fb4SMasahiro Yamada #define UMC_INITSET 0x00000014 63*107b3fb4SMasahiro Yamada #define UMC_INITSTAT 0x00000018 64*107b3fb4SMasahiro Yamada #define UMC_DRMMR0 0x0000001C 65*107b3fb4SMasahiro Yamada #define UMC_DRMMR1 0x00000020 66*107b3fb4SMasahiro Yamada #define UMC_DRMMR2 0x00000024 67*107b3fb4SMasahiro Yamada #define UMC_DRMMR3 0x00000028 68*107b3fb4SMasahiro Yamada #define UMC_SPCCTLA 0x00000030 69*107b3fb4SMasahiro Yamada #define UMC_SPCCTLB 0x00000034 70*107b3fb4SMasahiro Yamada #define UMC_SPCSETA 0x00000038 71*107b3fb4SMasahiro Yamada #define UMC_SPCSETB 0x0000003C 72*107b3fb4SMasahiro Yamada #define UMC_SPCSETC 0x00000040 73*107b3fb4SMasahiro Yamada #define UMC_SPCSETD 0x00000044 74*107b3fb4SMasahiro Yamada #define UMC_SPCSTATA 0x00000050 75*107b3fb4SMasahiro Yamada #define UMC_SPCSTATB 0x00000054 76*107b3fb4SMasahiro Yamada #define UMC_SPCSTATC 0x00000058 77*107b3fb4SMasahiro Yamada #define UMC_ACSSETA 0x00000060 78*107b3fb4SMasahiro Yamada #define UMC_FLOWCTLA 0x00000400 79*107b3fb4SMasahiro Yamada #define UMC_FLOWCTLB 0x00000404 80*107b3fb4SMasahiro Yamada #define UMC_FLOWCTLC 0x00000408 81*107b3fb4SMasahiro Yamada #define UMC_FLOWCTLG 0x00000508 82*107b3fb4SMasahiro Yamada #define UMC_RDATACTL_D0 0x00000600 83*107b3fb4SMasahiro Yamada #define UMC_WDATACTL_D0 0x00000604 84*107b3fb4SMasahiro Yamada #define UMC_RDATACTL_D1 0x00000608 85*107b3fb4SMasahiro Yamada #define UMC_WDATACTL_D1 0x0000060C 86*107b3fb4SMasahiro Yamada #define UMC_DATASET 0x00000610 87*107b3fb4SMasahiro Yamada #define UMC_DCCGCTL 0x00000720 88*107b3fb4SMasahiro Yamada #define UMC_DICGCTLA 0x00000724 89*107b3fb4SMasahiro Yamada #define UMC_DICGCTLB 0x00000728 90*107b3fb4SMasahiro Yamada #define UMC_DIOCTLA 0x00000C00 91*107b3fb4SMasahiro Yamada #define UMC_DFICUPDCTLA 0x00000C20 92*107b3fb4SMasahiro Yamada 93*107b3fb4SMasahiro Yamada #ifndef __ASSEMBLY__ 94*107b3fb4SMasahiro Yamada 95*107b3fb4SMasahiro Yamada #include <linux/types.h> 96*107b3fb4SMasahiro Yamada 97*107b3fb4SMasahiro Yamada static inline void umc_polling(u32 address, u32 expval, u32 mask) 98*107b3fb4SMasahiro Yamada { 99*107b3fb4SMasahiro Yamada u32 nmask = ~mask; 100*107b3fb4SMasahiro Yamada u32 data; 101*107b3fb4SMasahiro Yamada do { 102*107b3fb4SMasahiro Yamada data = readl(address) & nmask; 103*107b3fb4SMasahiro Yamada } while (data != expval); 104*107b3fb4SMasahiro Yamada } 105*107b3fb4SMasahiro Yamada 106*107b3fb4SMasahiro Yamada static inline void umc_dram_init_start(void __iomem *dramcont) 107*107b3fb4SMasahiro Yamada { 108*107b3fb4SMasahiro Yamada writel(0x00000002, dramcont + UMC_INITSET); 109*107b3fb4SMasahiro Yamada } 110*107b3fb4SMasahiro Yamada 111*107b3fb4SMasahiro Yamada static inline void umc_dram_init_poll(void __iomem *dramcont) 112*107b3fb4SMasahiro Yamada { 113*107b3fb4SMasahiro Yamada while ((readl(dramcont + UMC_INITSTAT) & 0x00000002)) 114*107b3fb4SMasahiro Yamada ; 115*107b3fb4SMasahiro Yamada } 116*107b3fb4SMasahiro Yamada 117*107b3fb4SMasahiro Yamada #endif 118*107b3fb4SMasahiro Yamada 119*107b3fb4SMasahiro Yamada #endif 120