1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2011-2014 Panasonic Corporation
4  * Copyright (C) 2015-2016 Socionext Inc.
5  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
6  */
7 
8 #include <common.h>
9 #include <linux/errno.h>
10 #include <linux/io.h>
11 #include <linux/sizes.h>
12 #include <asm/processor.h>
13 
14 #include "../init.h"
15 #include "ddrphy-init.h"
16 #include "umc-regs.h"
17 
18 #define DRAM_CH_NR	2
19 
20 enum dram_freq {
21 	DRAM_FREQ_1333M,
22 	DRAM_FREQ_1600M,
23 	DRAM_FREQ_NR,
24 };
25 
26 enum dram_size {
27 	DRAM_SZ_128M,
28 	DRAM_SZ_256M,
29 	DRAM_SZ_NR,
30 };
31 
32 static u32 umc_cmdctla_plus[DRAM_FREQ_NR] = {0x45990b11, 0x36bb0f17};
33 static u32 umc_cmdctlb_plus[DRAM_FREQ_NR] = {0x16958924, 0x18c6aa24};
34 static u32 umc_spcctla[DRAM_FREQ_NR][DRAM_SZ_NR] = {
35 	{0x00240512, 0x00350512},
36 	{0x002b0617, 0x003f0617},
37 };
38 static u32 umc_spcctlb[DRAM_FREQ_NR] = {0x00ff0006, 0x00ff0008};
39 static u32 umc_rdatactl[DRAM_FREQ_NR] = {0x000a00ac, 0x000c00ae};
40 
41 static int umc_get_rank(int ch)
42 {
43 	return ch;	/* ch0: rank0, ch1: rank1 for this SoC */
44 }
45 
46 static void umc_start_ssif(void __iomem *ssif_base)
47 {
48 	writel(0x00000000, ssif_base + 0x0000b004);
49 	writel(0xffffffff, ssif_base + 0x0000c004);
50 	writel(0x000fffcf, ssif_base + 0x0000c008);
51 	writel(0x00000001, ssif_base + 0x0000b000);
52 	writel(0x00000001, ssif_base + 0x0000c000);
53 	writel(0x03010101, ssif_base + UMC_MDMCHSEL);
54 	writel(0x03010100, ssif_base + UMC_DMDCHSEL);
55 
56 	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
57 	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
58 	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
59 	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
60 	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
61 	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
62 	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
63 	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
64 	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
65 	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
66 
67 	writel(0x00000001, ssif_base + UMC_CPURST);
68 	writel(0x00000001, ssif_base + UMC_IDSRST);
69 	writel(0x00000001, ssif_base + UMC_IXMRST);
70 	writel(0x00000001, ssif_base + UMC_MDMRST);
71 	writel(0x00000001, ssif_base + UMC_MDDRST);
72 	writel(0x00000001, ssif_base + UMC_SIORST);
73 	writel(0x00000001, ssif_base + UMC_VIORST);
74 	writel(0x00000001, ssif_base + UMC_FRCRST);
75 	writel(0x00000001, ssif_base + UMC_RGLRST);
76 	writel(0x00000001, ssif_base + UMC_AIORST);
77 	writel(0x00000001, ssif_base + UMC_DMDRST);
78 }
79 
80 static int umc_dramcont_init(void __iomem *dc_base, void __iomem *ca_base,
81 			     int freq, unsigned long size, bool ddr3plus)
82 {
83 	enum dram_freq freq_e;
84 	enum dram_size size_e;
85 
86 	if (!ddr3plus) {
87 		pr_err("DDR3 standard is not supported\n");
88 		return -EINVAL;
89 	}
90 
91 	switch (freq) {
92 	case 1333:
93 		freq_e = DRAM_FREQ_1333M;
94 		break;
95 	case 1600:
96 		freq_e = DRAM_FREQ_1600M;
97 		break;
98 	default:
99 		pr_err("unsupported DRAM frequency %d MHz\n", freq);
100 		return -EINVAL;
101 	}
102 
103 	switch (size) {
104 	case 0:
105 		return 0;
106 	case SZ_128M:
107 		size_e = DRAM_SZ_128M;
108 		break;
109 	case SZ_256M:
110 		size_e = DRAM_SZ_256M;
111 		break;
112 	default:
113 		pr_err("unsupported DRAM size 0x%08lx\n", size);
114 		return -EINVAL;
115 	}
116 
117 	writel(umc_cmdctla_plus[freq_e], dc_base + UMC_CMDCTLA);
118 	writel(umc_cmdctlb_plus[freq_e], dc_base + UMC_CMDCTLB);
119 	writel(umc_spcctla[freq_e][size_e], dc_base + UMC_SPCCTLA);
120 	writel(umc_spcctlb[freq_e], dc_base + UMC_SPCCTLB);
121 	writel(umc_rdatactl[freq_e], dc_base + UMC_RDATACTL_D0);
122 	writel(0x04060806, dc_base + UMC_WDATACTL_D0);
123 	writel(0x04a02000, dc_base + UMC_DATASET);
124 	writel(0x00000000, ca_base + 0x2300);
125 	writel(0x00400020, dc_base + UMC_DCCGCTL);
126 	writel(0x00000003, dc_base + 0x7000);
127 	writel(0x0000000f, dc_base + 0x8000);
128 	writel(0x000000c3, dc_base + 0x8004);
129 	writel(0x00000071, dc_base + 0x8008);
130 	writel(0x0000003b, dc_base + UMC_DICGCTLA);
131 	writel(0x020a0808, dc_base + UMC_DICGCTLB);
132 	writel(0x00000004, dc_base + UMC_FLOWCTLG);
133 	writel(0x80000201, ca_base + 0xc20);
134 	writel(0x0801e01e, dc_base + UMC_FLOWCTLA);
135 	writel(0x00200000, dc_base + UMC_FLOWCTLB);
136 	writel(0x00004444, dc_base + UMC_FLOWCTLC);
137 	writel(0x200a0a00, dc_base + UMC_SPCSETB);
138 	writel(0x00000000, dc_base + UMC_SPCSETD);
139 	writel(0x00000520, dc_base + UMC_DFICUPDCTLA);
140 
141 	return 0;
142 }
143 
144 static int umc_ch_init(void __iomem *dc_base, void __iomem *ca_base,
145 		       int freq, unsigned long size, bool ddr3plus, int ch)
146 {
147 	void __iomem *phy_base = dc_base + 0x00001000;
148 	int ret;
149 
150 	writel(UMC_INITSET_INIT1EN, dc_base + UMC_INITSET);
151 	while (readl(dc_base + UMC_INITSTAT) & UMC_INITSTAT_INIT1ST)
152 		cpu_relax();
153 
154 	writel(0x00000101, dc_base + UMC_DIOCTLA);
155 
156 	ret = uniphier_ld4_ddrphy_init(phy_base, freq, ddr3plus);
157 	if (ret)
158 		return ret;
159 
160 	ddrphy_prepare_training(phy_base, umc_get_rank(ch));
161 	ret = ddrphy_training(phy_base);
162 	if (ret)
163 		return ret;
164 
165 	return umc_dramcont_init(dc_base, ca_base, freq, size, ddr3plus);
166 }
167 
168 int uniphier_ld4_umc_init(const struct uniphier_board_data *bd)
169 {
170 	void __iomem *umc_base = (void __iomem *)0x5b800000;
171 	void __iomem *ca_base = umc_base + 0x00001000;
172 	void __iomem *dc_base = umc_base + 0x00400000;
173 	void __iomem *ssif_base = umc_base;
174 	int ch, ret;
175 
176 	for (ch = 0; ch < DRAM_CH_NR; ch++) {
177 		ret = umc_ch_init(dc_base, ca_base, bd->dram_freq,
178 				  bd->dram_ch[ch].size,
179 				  !!(bd->flags & UNIPHIER_BD_DDR3PLUS), ch);
180 		if (ret) {
181 			pr_err("failed to initialize UMC ch%d\n", ch);
182 			return ret;
183 		}
184 
185 		ca_base += 0x00001000;
186 		dc_base += 0x00200000;
187 	}
188 
189 	umc_start_ssif(ssif_base);
190 
191 	return 0;
192 }
193