1 /*
2  * UniPhier DDR PHY registers
3  *
4  * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #ifndef ARCH_DDRPHY_REGS_H
10 #define ARCH_DDRPHY_REGS_H
11 
12 #include <linux/bitops.h>
13 #include <linux/compiler.h>
14 #include <linux/types.h>
15 
16 #ifndef __ASSEMBLY__
17 
18 struct ddrphy {
19 	u32 ridr;		/* Revision Identification Register */
20 	u32 pir;		/* PHY Initialixation Register */
21 	u32 pgcr[2];		/* PHY General Configuration Register */
22 	u32 pgsr[2];		/* PHY General Status Register */
23 	u32 pllcr;		/* PLL Control Register */
24 	u32 ptr[5];		/* PHY Timing Register */
25 	u32 acmdlr;		/* AC Master Delay Line Register */
26 	u32 acbdlr;		/* AC Bit Delay Line Register */
27 	u32 aciocr;		/* AC I/O Configuration Register */
28 	u32 dxccr;		/* DATX8 Common Configuration Register */
29 	u32 dsgcr;		/* DDR System General Configuration Register */
30 	u32 dcr;		/* DRAM Configuration Register */
31 	u32 dtpr[3];		/* DRAM Timing Parameters Register */
32 	u32 mr0;		/* Mode Register 0 */
33 	u32 mr1;		/* Mode Register 1 */
34 	u32 mr2;		/* Mode Register 2 */
35 	u32 mr3;		/* Mode Register 3 */
36 	u32 odtcr;		/* ODT Configuration Register */
37 	u32 dtcr;		/* Data Training Configuration Register */
38 	u32 dtar[4];		/* Data Training Address Register */
39 	u32 dtdr[2];		/* Data Training Data Register */
40 	u32 dtedr[2];		/* Data Training Eye Data Register */
41 	u32 pgcr2;		/* PHY General Configuration Register 2 */
42 	u32 rsv0[8];		/* Reserved */
43 	u32 rdimmgcr[2];	/* RDIMM General Configuration Register */
44 	u32 rdimmcr0[2];	/* RDIMM Control Register */
45 	u32 dcuar;		/* DCU Address Register */
46 	u32 dcudr;		/* DCU Data Register */
47 	u32 dcurr;		/* DCU Run Register */
48 	u32 dculr;		/* DCU Loop Register */
49 	u32 dcugcr;		/* DCU General Configuration Register */
50 	u32 dcutpr;		/* DCU Timing Parameters Register */
51 	u32 dcusr[2];		/* DCU Status Register */
52 	u32 rsv1[8];		/* Reserved */
53 	u32 bistrr;		/* BIST Run Register */
54 	u32 bistwcr;		/* BIST Word Count Register */
55 	u32 bistmskr[3];	/* BIST Mask Register */
56 	u32 bistlsr;		/* BIST LFSR Sed Register */
57 	u32 bistar[3];		/* BIST Address Register */
58 	u32 bistudpr;		/* BIST User Data Pattern Register */
59 	u32 bistgsr;		/* BIST General Status Register */
60 	u32 bistwer;		/* BIST Word Error Register */
61 	u32 bistber[4];		/* BIST Bit Error Register */
62 	u32 bistwcsr;		/* BIST Word Count Status Register */
63 	u32 bistfwr[3];		/* BIST Fail Word Register */
64 	u32 rsv2[10];		/* Reserved */
65 	u32 gpr[2];		/* General Purpose Register */
66 	struct ddrphy_zq {	/* ZQ */
67 		u32 cr[2];	/* Impedance Control Register */
68 		u32 sr[2];	/* Impedance Status Register */
69 	} zq[4];
70 	struct ddrphy_datx8 {	/* DATX8 */
71 		u32 gcr;	/* General Configuration Register */
72 		u32 gsr[2];	/* General Status Register */
73 		u32 bdlr[5];	/* Bit Delay Line Register */
74 		u32 lcdlr[3];	/* Local Calibrated Delay Line Register */
75 		u32 mdlr;	/* Master Delay Line Register */
76 		u32 gtr;	/* General Timing Register */
77 		u32 gsr2;	/* General Status Register 2 */
78 		u32 rsv[2];	/* Reserved */
79 	} dx[9];
80 };
81 
82 #endif /* __ASSEMBLY__ */
83 
84 #define PIR_INIT		BIT(0)		/* Initialization Trigger */
85 #define PIR_ZCAL		BIT(1)		/* Impedance Calibration */
86 #define PIR_PLLINIT		BIT(4)		/* PLL Initialization */
87 #define PIR_DCAL		BIT(5)		/* DDL Calibration */
88 #define PIR_PHYRST		BIT(6)		/* PHY Reset */
89 #define PIR_DRAMRST		BIT(7)		/* DRAM Reset */
90 #define PIR_DRAMINIT		BIT(8)		/* DRAM Initialization */
91 #define PIR_WL			BIT(9)		/* Write Leveling */
92 #define PIR_QSGATE		BIT(10)		/* Read DQS Gate Training */
93 #define PIR_WLADJ		BIT(11)		/* Write Leveling Adjust */
94 #define PIR_RDDSKW		BIT(12)		/* Read Data Bit Deskew */
95 #define PIR_WRDSKW		BIT(13)		/* Write Data Bit Deskew */
96 #define PIR_RDEYE		BIT(14)		/* Read Data Eye Training */
97 #define PIR_WREYE		BIT(15)		/* Write Data Eye Training */
98 #define PIR_LOCKBYP		BIT(28)		/* PLL Lock Bypass */
99 #define PIR_DCALBYP		BIT(29)		/* DDL Calibration Bypass */
100 #define PIR_ZCALBYP		BIT(30)		/* Impedance Calib Bypass */
101 #define PIR_INITBYP		BIT(31)		/* Initialization Bypass */
102 
103 #define PGSR0_IDONE		BIT(0)		/* Initialization Done */
104 #define PGSR0_PLDONE		BIT(1)		/* PLL Lock Done */
105 #define PGSR0_DCDONE		BIT(2)		/* DDL Calibration Done */
106 #define PGSR0_ZCDONE		BIT(3)		/* Impedance Calibration Done */
107 #define PGSR0_DIDONE		BIT(4)		/* DRAM Initialization Done */
108 #define PGSR0_WLDONE		BIT(5)		/* Write Leveling Done */
109 #define PGSR0_QSGDONE		BIT(6)		/* DQS Gate Training Done */
110 #define PGSR0_WLADONE		BIT(7)		/* Write Leveling Adjust Done */
111 #define PGSR0_RDDONE		BIT(8)		/* Read Bit Deskew Done */
112 #define PGSR0_WDDONE		BIT(9)		/* Write Bit Deskew Done */
113 #define PGSR0_REDONE		BIT(10)		/* Read Eye Training Done */
114 #define PGSR0_WEDONE		BIT(11)		/* Write Eye Training Done */
115 #define PGSR0_IERR		BIT(16)		/* Initialization Error */
116 #define PGSR0_PLERR		BIT(17)		/* PLL Lock Error */
117 #define PGSR0_DCERR		BIT(18)		/* DDL Calibration Error */
118 #define PGSR0_ZCERR		BIT(19)		/* Impedance Calib Error */
119 #define PGSR0_DIERR		BIT(20)		/* DRAM Initialization Error */
120 #define PGSR0_WLERR		BIT(21)		/* Write Leveling Error */
121 #define PGSR0_QSGERR		BIT(22)		/* DQS Gate Training Error */
122 #define PGSR0_WLAERR		BIT(23)		/* Write Leveling Adj Error */
123 #define PGSR0_RDERR		BIT(24)		/* Read Bit Deskew Error */
124 #define PGSR0_WDERR		BIT(25)		/* Write Bit Deskew Error */
125 #define PGSR0_REERR		BIT(26)		/* Read Eye Training Error */
126 #define PGSR0_WEERR		BIT(27)		/* Write Eye Training Error */
127 #define PGSR0_DTERR_SHIFT	28		/* Data Training Error Status*/
128 #define PGSR0_DTERR		(7 << (PGSR0_DTERR_SHIFT))
129 #define PGSR0_APLOCK		BIT(31)		/* AC PLL Lock */
130 
131 #define DXCCR_DQSRES_OPEN	(0 << 5)
132 #define DXCCR_DQSRES_688_OHM	(1 << 5)
133 #define DXCCR_DQSRES_611_OHM	(2 << 5)
134 #define DXCCR_DQSRES_550_OHM	(3 << 5)
135 #define DXCCR_DQSRES_500_OHM	(4 << 5)
136 #define DXCCR_DQSRES_458_OHM	(5 << 5)
137 #define DXCCR_DQSRES_393_OHM	(6 << 5)
138 #define DXCCR_DQSRES_344_OHM	(7 << 5)
139 
140 #define DXCCR_DQSNRES_OPEN	(0 << 9)
141 #define DXCCR_DQSNRES_688_OHM	(1 << 9)
142 #define DXCCR_DQSNRES_611_OHM	(2 << 9)
143 #define DXCCR_DQSNRES_550_OHM	(3 << 9)
144 #define DXCCR_DQSNRES_500_OHM	(4 << 9)
145 #define DXCCR_DQSNRES_458_OHM	(5 << 9)
146 #define DXCCR_DQSNRES_393_OHM	(6 << 9)
147 #define DXCCR_DQSNRES_344_OHM	(7 << 9)
148 
149 #define DTCR_DTRANK_SHIFT	4		/* Data Training Rank */
150 #define DTCR_DTRANK_MASK	(0x3 << (DTCR_DTRANK_SHIFT))
151 #define DTCR_DTMPR		BIT(6)		/* Data Training using MPR */
152 #define DTCR_RANKEN_SHIFT	24		/* Rank Enable */
153 #define DTCR_RANKEN_MASK	(0xf << (DTCR_RANKEN_SHIFT))
154 
155 #define DXGCR_WLRKEN_SHIFT	26		/* Write Level Rank Enable */
156 #define DXGCR_WLRKEN_MASK	(0xf << (DXGCR_WLRKEN_SHIFT))
157 
158 /* SoC-specific parameters */
159 #define NR_DATX8_PER_DDRPHY	2
160 
161 #if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) || \
162 	defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
163 #define NR_DDRPHY_PER_CH		1
164 #else
165 #define NR_DDRPHY_PER_CH		2
166 #endif
167 
168 #define NR_DDRCH		2
169 
170 #define DDRPHY_BASE(ch, phy)	(0x5bc01000 + 0x200000 * (ch) + 0x1000 * (phy))
171 
172 #ifndef __ASSEMBLY__
173 int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, bool ddr3plus);
174 void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank);
175 int ddrphy_training(struct ddrphy __iomem *phy);
176 #endif
177 
178 #endif /* ARCH_DDRPHY_REGS_H */
179