1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 2ea65c980SMasahiro Yamada /* 36dd34ae4SMasahiro Yamada * Copyright (C) 2014 Panasonic Corporation 46dd34ae4SMasahiro Yamada * Copyright (C) 2015-2016 Socionext Inc. 5ea65c980SMasahiro Yamada */ 6ea65c980SMasahiro Yamada 7dd74b945SMasahiro Yamada #include <linux/bitops.h> 80f4ec05bSMasahiro Yamada #include <linux/errno.h> 9ea65c980SMasahiro Yamada #include <linux/io.h> 10dd74b945SMasahiro Yamada #include <linux/printk.h> 11ea65c980SMasahiro Yamada 126dd34ae4SMasahiro Yamada #include "ddrphy-init.h" 13ea65c980SMasahiro Yamada #include "ddrphy-regs.h" 14ea65c980SMasahiro Yamada 15ea65c980SMasahiro Yamada enum dram_freq { 16ea65c980SMasahiro Yamada DRAM_FREQ_1333M, 17ea65c980SMasahiro Yamada DRAM_FREQ_1600M, 18ea65c980SMasahiro Yamada DRAM_FREQ_NR, 19ea65c980SMasahiro Yamada }; 20ea65c980SMasahiro Yamada 21ea65c980SMasahiro Yamada static u32 ddrphy_ptr0[DRAM_FREQ_NR] = {0x0a806844, 0x0c807d04}; 22ea65c980SMasahiro Yamada static u32 ddrphy_ptr1[DRAM_FREQ_NR] = {0x208e0124, 0x2710015E}; 23ea65c980SMasahiro Yamada static u32 ddrphy_ptr3[DRAM_FREQ_NR] = {0x0f051616, 0x12061A80}; 24ea65c980SMasahiro Yamada static u32 ddrphy_ptr4[DRAM_FREQ_NR] = {0x06ae08d6, 0x08027100}; 25ea65c980SMasahiro Yamada static u32 ddrphy_dtpr0[DRAM_FREQ_NR] = {0x85589955, 0x999cbb66}; 26ea65c980SMasahiro Yamada static u32 ddrphy_dtpr1[DRAM_FREQ_NR] = {0x1a8363c0, 0x1a878400}; 27ea65c980SMasahiro Yamada static u32 ddrphy_dtpr2[DRAM_FREQ_NR] = {0x5002c200, 0xa00214f8}; 28ea65c980SMasahiro Yamada static u32 ddrphy_mr0[DRAM_FREQ_NR] = {0x00000b51, 0x00000d71}; 29ea65c980SMasahiro Yamada static u32 ddrphy_mr2[DRAM_FREQ_NR] = {0x00000290, 0x00000298}; 30ea65c980SMasahiro Yamada 316dd34ae4SMasahiro Yamada int uniphier_ld4_ddrphy_init(void __iomem *phy_base, int freq, bool ddr3plus) 32ea65c980SMasahiro Yamada { 33ea65c980SMasahiro Yamada enum dram_freq freq_e; 34ea65c980SMasahiro Yamada u32 tmp; 35ea65c980SMasahiro Yamada 36ea65c980SMasahiro Yamada switch (freq) { 37ea65c980SMasahiro Yamada case 1333: 38ea65c980SMasahiro Yamada freq_e = DRAM_FREQ_1333M; 39ea65c980SMasahiro Yamada break; 40ea65c980SMasahiro Yamada case 1600: 41ea65c980SMasahiro Yamada freq_e = DRAM_FREQ_1600M; 42ea65c980SMasahiro Yamada break; 43ea65c980SMasahiro Yamada default: 44dd74b945SMasahiro Yamada pr_err("unsupported DRAM frequency %d MHz\n", freq); 45ea65c980SMasahiro Yamada return -EINVAL; 46ea65c980SMasahiro Yamada } 47ea65c980SMasahiro Yamada 486dd34ae4SMasahiro Yamada writel(0x0300c473, phy_base + PHY_PGCR1); 496dd34ae4SMasahiro Yamada writel(ddrphy_ptr0[freq_e], phy_base + PHY_PTR0); 506dd34ae4SMasahiro Yamada writel(ddrphy_ptr1[freq_e], phy_base + PHY_PTR1); 516dd34ae4SMasahiro Yamada writel(0x00083DEF, phy_base + PHY_PTR2); 526dd34ae4SMasahiro Yamada writel(ddrphy_ptr3[freq_e], phy_base + PHY_PTR3); 536dd34ae4SMasahiro Yamada writel(ddrphy_ptr4[freq_e], phy_base + PHY_PTR4); 546dd34ae4SMasahiro Yamada writel(0xF004001A, phy_base + PHY_DSGCR); 55ea65c980SMasahiro Yamada 56ea65c980SMasahiro Yamada /* change the value of the on-die pull-up/pull-down registors */ 576dd34ae4SMasahiro Yamada tmp = readl(phy_base + PHY_DXCCR); 58ea65c980SMasahiro Yamada tmp &= ~0x0ee0; 596dd34ae4SMasahiro Yamada tmp |= PHY_DXCCR_DQSNRES_688_OHM | PHY_DXCCR_DQSRES_688_OHM; 606dd34ae4SMasahiro Yamada writel(tmp, phy_base + PHY_DXCCR); 61ea65c980SMasahiro Yamada 626dd34ae4SMasahiro Yamada writel(0x0000040B, phy_base + PHY_DCR); 636dd34ae4SMasahiro Yamada writel(ddrphy_dtpr0[freq_e], phy_base + PHY_DTPR0); 646dd34ae4SMasahiro Yamada writel(ddrphy_dtpr1[freq_e], phy_base + PHY_DTPR1); 656dd34ae4SMasahiro Yamada writel(ddrphy_dtpr2[freq_e], phy_base + PHY_DTPR2); 666dd34ae4SMasahiro Yamada writel(ddrphy_mr0[freq_e], phy_base + PHY_MR0); 676dd34ae4SMasahiro Yamada writel(0x00000006, phy_base + PHY_MR1); 686dd34ae4SMasahiro Yamada writel(ddrphy_mr2[freq_e], phy_base + PHY_MR2); 696dd34ae4SMasahiro Yamada writel(ddr3plus ? 0x00000800 : 0x00000000, phy_base + PHY_MR3); 70ea65c980SMasahiro Yamada 716dd34ae4SMasahiro Yamada while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE)) 72ea65c980SMasahiro Yamada ; 73ea65c980SMasahiro Yamada 746dd34ae4SMasahiro Yamada writel(0x0300C473, phy_base + PHY_PGCR1); 756dd34ae4SMasahiro Yamada writel(0x0000005D, phy_base + PHY_ZQ_BASE + PHY_ZQ_CR1); 76ea65c980SMasahiro Yamada 77ea65c980SMasahiro Yamada return 0; 78ea65c980SMasahiro Yamada } 79