1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 215607d0dSMasahiro Yamada /* 315607d0dSMasahiro Yamada * UniPhier DDR MultiPHY registers 415607d0dSMasahiro Yamada * 5fada9eafSMasahiro Yamada * Copyright (C) 2015-2017 Socionext Inc. 615607d0dSMasahiro Yamada */ 715607d0dSMasahiro Yamada 8fada9eafSMasahiro Yamada #ifndef UNIPHIER_DDRMPHY_REGS_H 9fada9eafSMasahiro Yamada #define UNIPHIER_DDRMPHY_REGS_H 1015607d0dSMasahiro Yamada 1115607d0dSMasahiro Yamada #include <linux/bitops.h> 1215607d0dSMasahiro Yamada 13fada9eafSMasahiro Yamada #define MPHY_SHIFT 2 1415607d0dSMasahiro Yamada 15fada9eafSMasahiro Yamada #define MPHY_RIDR (0x000 << MPHY_SHIFT) 16fada9eafSMasahiro Yamada #define MPHY_PIR (0x001 << MPHY_SHIFT) 17fada9eafSMasahiro Yamada #define MPHY_PIR_INIT BIT(0) /* Initialization Trigger */ 18fada9eafSMasahiro Yamada #define MPHY_PIR_ZCAL BIT(1) /* Impedance Calibration */ 19fada9eafSMasahiro Yamada #define MPHY_PIR_PLLINIT BIT(4) /* PLL Initialization */ 20fada9eafSMasahiro Yamada #define MPHY_PIR_DCAL BIT(5) /* DDL Calibration */ 21fada9eafSMasahiro Yamada #define MPHY_PIR_PHYRST BIT(6) /* PHY Reset */ 22fada9eafSMasahiro Yamada #define MPHY_PIR_DRAMRST BIT(7) /* DRAM Reset */ 23fada9eafSMasahiro Yamada #define MPHY_PIR_DRAMINIT BIT(8) /* DRAM Initialization */ 24fada9eafSMasahiro Yamada #define MPHY_PIR_WL BIT(9) /* Write Leveling */ 25fada9eafSMasahiro Yamada #define MPHY_PIR_QSGATE BIT(10) /* Read DQS Gate Training */ 26fada9eafSMasahiro Yamada #define MPHY_PIR_WLADJ BIT(11) /* Write Leveling Adjust */ 27fada9eafSMasahiro Yamada #define MPHY_PIR_RDDSKW BIT(12) /* Read Data Bit Deskew */ 28fada9eafSMasahiro Yamada #define MPHY_PIR_WRDSKW BIT(13) /* Write Data Bit Deskew */ 29fada9eafSMasahiro Yamada #define MPHY_PIR_RDEYE BIT(14) /* Read Data Eye Training */ 30fada9eafSMasahiro Yamada #define MPHY_PIR_WREYE BIT(15) /* Write Data Eye Training */ 31fada9eafSMasahiro Yamada #define MPHY_PIR_ZCALBYP BIT(30) /* Impedance Calib Bypass */ 32fada9eafSMasahiro Yamada #define MPHY_PIR_INITBYP BIT(31) /* Initialization Bypass */ 33fada9eafSMasahiro Yamada #define MPHY_PGCR0 (0x002 << MPHY_SHIFT) 34fada9eafSMasahiro Yamada #define MPHY_PGCR0_PHYFRST BIT(26) /* PHY FIFO Reset */ 35fada9eafSMasahiro Yamada #define MPHY_PGCR1 (0x003 << MPHY_SHIFT) 36fada9eafSMasahiro Yamada #define MPHY_PGCR1_INHVT BIT(26) /* VT Calculation Inhibit */ 37fada9eafSMasahiro Yamada #define MPHY_PGCR2 (0x004 << MPHY_SHIFT) 38fada9eafSMasahiro Yamada #define MPHY_PGCR2_DUALCHN BIT(28) /* Dual Channel Configuration*/ 39fada9eafSMasahiro Yamada #define MPHY_PGCR2_ACPDDC BIT(29) /* AC Power-Down with Dual Ch*/ 40fada9eafSMasahiro Yamada #define MPHY_PGCR3 (0x005 << MPHY_SHIFT) 41fada9eafSMasahiro Yamada #define MPHY_PGSR0 (0x006 << MPHY_SHIFT) 42fada9eafSMasahiro Yamada #define MPHY_PGSR0_IDONE BIT(0) /* Initialization Done */ 43fada9eafSMasahiro Yamada #define MPHY_PGSR0_PLDONE BIT(1) /* PLL Lock Done */ 44fada9eafSMasahiro Yamada #define MPHY_PGSR0_DCDONE BIT(2) /* DDL Calibration Done */ 45fada9eafSMasahiro Yamada #define MPHY_PGSR0_ZCDONE BIT(3) /* Impedance Calibration Done */ 46fada9eafSMasahiro Yamada #define MPHY_PGSR0_DIDONE BIT(4) /* DRAM Initialization Done */ 47fada9eafSMasahiro Yamada #define MPHY_PGSR0_WLDONE BIT(5) /* Write Leveling Done */ 48fada9eafSMasahiro Yamada #define MPHY_PGSR0_QSGDONE BIT(6) /* DQS Gate Training Done */ 49fada9eafSMasahiro Yamada #define MPHY_PGSR0_WLADONE BIT(7) /* Write Leveling Adjust Done */ 50fada9eafSMasahiro Yamada #define MPHY_PGSR0_RDDONE BIT(8) /* Read Bit Deskew Done */ 51fada9eafSMasahiro Yamada #define MPHY_PGSR0_WDDONE BIT(9) /* Write Bit Deskew Done */ 52fada9eafSMasahiro Yamada #define MPHY_PGSR0_REDONE BIT(10) /* Read Eye Training Done */ 53fada9eafSMasahiro Yamada #define MPHY_PGSR0_WEDONE BIT(11) /* Write Eye Training Done */ 54fada9eafSMasahiro Yamada #define MPHY_PGSR0_ZCERR BIT(20) /* Impedance Calib Error */ 55fada9eafSMasahiro Yamada #define MPHY_PGSR0_WLERR BIT(21) /* Write Leveling Error */ 56fada9eafSMasahiro Yamada #define MPHY_PGSR0_QSGERR BIT(22) /* DQS Gate Training Error */ 57fada9eafSMasahiro Yamada #define MPHY_PGSR0_WLAERR BIT(23) /* Write Leveling Adj Error */ 58fada9eafSMasahiro Yamada #define MPHY_PGSR0_RDERR BIT(24) /* Read Bit Deskew Error */ 59fada9eafSMasahiro Yamada #define MPHY_PGSR0_WDERR BIT(25) /* Write Bit Deskew Error */ 60fada9eafSMasahiro Yamada #define MPHY_PGSR0_REERR BIT(26) /* Read Eye Training Error */ 61fada9eafSMasahiro Yamada #define MPHY_PGSR0_WEERR BIT(27) /* Write Eye Training Error */ 62fada9eafSMasahiro Yamada #define MPHY_PGSR1 (0x007 << MPHY_SHIFT) 63fada9eafSMasahiro Yamada #define MPHY_PGSR1_VTSTOP BIT(30) /* VT Stop */ 64fada9eafSMasahiro Yamada #define MPHY_PLLCR (0x008 << MPHY_SHIFT) 65fada9eafSMasahiro Yamada #define MPHY_PTR0 (0x009 << MPHY_SHIFT) 66fada9eafSMasahiro Yamada #define MPHY_PTR1 (0x00A << MPHY_SHIFT) 67fada9eafSMasahiro Yamada #define MPHY_PTR2 (0x00B << MPHY_SHIFT) 68fada9eafSMasahiro Yamada #define MPHY_PTR3 (0x00C << MPHY_SHIFT) 69fada9eafSMasahiro Yamada #define MPHY_PTR4 (0x00D << MPHY_SHIFT) 70fada9eafSMasahiro Yamada #define MPHY_ACMDLR (0x00E << MPHY_SHIFT) 71fada9eafSMasahiro Yamada #define MPHY_ACLCDLR (0x00F << MPHY_SHIFT) 72fada9eafSMasahiro Yamada #define MPHY_ACBDLR0 (0x010 << MPHY_SHIFT) 73fada9eafSMasahiro Yamada #define MPHY_ACBDLR1 (0x011 << MPHY_SHIFT) 74fada9eafSMasahiro Yamada #define MPHY_ACBDLR2 (0x012 << MPHY_SHIFT) 75fada9eafSMasahiro Yamada #define MPHY_ACBDLR3 (0x013 << MPHY_SHIFT) 76fada9eafSMasahiro Yamada #define MPHY_ACBDLR4 (0x014 << MPHY_SHIFT) 77fada9eafSMasahiro Yamada #define MPHY_ACBDLR5 (0x015 << MPHY_SHIFT) 78fada9eafSMasahiro Yamada #define MPHY_ACBDLR6 (0x016 << MPHY_SHIFT) 79fada9eafSMasahiro Yamada #define MPHY_ACBDLR7 (0x017 << MPHY_SHIFT) 80fada9eafSMasahiro Yamada #define MPHY_ACBDLR8 (0x018 << MPHY_SHIFT) 81fada9eafSMasahiro Yamada #define MPHY_ACBDLR9 (0x019 << MPHY_SHIFT) 82fada9eafSMasahiro Yamada #define MPHY_ACIOCR0 (0x01A << MPHY_SHIFT) 83fada9eafSMasahiro Yamada #define MPHY_ACIOCR1 (0x01B << MPHY_SHIFT) 84fada9eafSMasahiro Yamada #define MPHY_ACIOCR2 (0x01C << MPHY_SHIFT) 85fada9eafSMasahiro Yamada #define MPHY_ACIOCR3 (0x01D << MPHY_SHIFT) 86fada9eafSMasahiro Yamada #define MPHY_ACIOCR4 (0x01E << MPHY_SHIFT) 87fada9eafSMasahiro Yamada #define MPHY_ACIOCR5 (0x01F << MPHY_SHIFT) 88fada9eafSMasahiro Yamada #define MPHY_DXCCR (0x020 << MPHY_SHIFT) 89fada9eafSMasahiro Yamada #define MPHY_DSGCR (0x021 << MPHY_SHIFT) 90fada9eafSMasahiro Yamada #define MPHY_DCR (0x022 << MPHY_SHIFT) 91fada9eafSMasahiro Yamada #define MPHY_DTPR0 (0x023 << MPHY_SHIFT) 92fada9eafSMasahiro Yamada #define MPHY_DTPR1 (0x024 << MPHY_SHIFT) 93fada9eafSMasahiro Yamada #define MPHY_DTPR2 (0x025 << MPHY_SHIFT) 94fada9eafSMasahiro Yamada #define MPHY_DTPR3 (0x026 << MPHY_SHIFT) 95fada9eafSMasahiro Yamada #define MPHY_MR0 (0x027 << MPHY_SHIFT) 96fada9eafSMasahiro Yamada #define MPHY_MR1 (0x028 << MPHY_SHIFT) 97fada9eafSMasahiro Yamada #define MPHY_MR2 (0x029 << MPHY_SHIFT) 98fada9eafSMasahiro Yamada #define MPHY_MR3 (0x02A << MPHY_SHIFT) 99fada9eafSMasahiro Yamada #define MPHY_ODTCR (0x02B << MPHY_SHIFT) 100fada9eafSMasahiro Yamada #define MPHY_DTCR (0x02C << MPHY_SHIFT) 101fada9eafSMasahiro Yamada #define MPHY_DTCR_RANKEN_SHIFT 24 /* Rank Enable */ 102fada9eafSMasahiro Yamada #define MPHY_DTCR_RANKEN_MASK (0xf << (MPHY_DTCR_RANKEN_SHIFT)) 103fada9eafSMasahiro Yamada #define MPHY_DTAR0 (0x02D << MPHY_SHIFT) 104fada9eafSMasahiro Yamada #define MPHY_DTAR1 (0x02E << MPHY_SHIFT) 105fada9eafSMasahiro Yamada #define MPHY_DTAR2 (0x02F << MPHY_SHIFT) 106fada9eafSMasahiro Yamada #define MPHY_DTAR3 (0x030 << MPHY_SHIFT) 107fada9eafSMasahiro Yamada #define MPHY_DTDR0 (0x031 << MPHY_SHIFT) 108fada9eafSMasahiro Yamada #define MPHY_DTDR1 (0x032 << MPHY_SHIFT) 109fada9eafSMasahiro Yamada #define MPHY_DTEDR0 (0x033 << MPHY_SHIFT) 110fada9eafSMasahiro Yamada #define MPHY_DTEDR1 (0x034 << MPHY_SHIFT) 111fada9eafSMasahiro Yamada #define MPHY_ZQCR (0x090 << MPHY_SHIFT) 112fada9eafSMasahiro Yamada #define MPHY_ZQCR_AVGEN BIT(16) /* Average Algorithm */ 113fada9eafSMasahiro Yamada #define MPHY_ZQCR_FORCE_ZCAL_VT_UPDATE BIT(27) /* force VT update */ 11415607d0dSMasahiro Yamada /* ZQ */ 115fada9eafSMasahiro Yamada #define MPHY_ZQ_BASE (0x091 << MPHY_SHIFT) 116fada9eafSMasahiro Yamada #define MPHY_ZQ_STRIDE (0x004 << MPHY_SHIFT) 117fada9eafSMasahiro Yamada #define MPHY_ZQ_PR (0x000 << MPHY_SHIFT) 118fada9eafSMasahiro Yamada #define MPHY_ZQ_DR (0x001 << MPHY_SHIFT) 119fada9eafSMasahiro Yamada #define MPHY_ZQ_SR (0x002 << MPHY_SHIFT) 12015607d0dSMasahiro Yamada /* DATX8 */ 121fada9eafSMasahiro Yamada #define MPHY_DX_BASE (0x0A0 << MPHY_SHIFT) 122fada9eafSMasahiro Yamada #define MPHY_DX_STRIDE (0x020 << MPHY_SHIFT) 123fada9eafSMasahiro Yamada #define MPHY_DX_GCR0 (0x000 << MPHY_SHIFT) 124fada9eafSMasahiro Yamada #define MPHY_DX_GCR0_WLRKEN_SHIFT 26 /* Write Level Rank Enable */ 125fada9eafSMasahiro Yamada #define MPHY_DX_GCR0_WLRKEN_MASK (0xf << (MPHY_DX_GCR0_WLRKEN_SHIFT)) 126fada9eafSMasahiro Yamada #define MPHY_DX_GCR1 (0x001 << MPHY_SHIFT) 127fada9eafSMasahiro Yamada #define MPHY_DX_GCR2 (0x002 << MPHY_SHIFT) 128fada9eafSMasahiro Yamada #define MPHY_DX_GCR3 (0x003 << MPHY_SHIFT) 129fada9eafSMasahiro Yamada #define MPHY_DX_GSR0 (0x004 << MPHY_SHIFT) 130fada9eafSMasahiro Yamada #define MPHY_DX_GSR1 (0x005 << MPHY_SHIFT) 131fada9eafSMasahiro Yamada #define MPHY_DX_GSR2 (0x006 << MPHY_SHIFT) 132fada9eafSMasahiro Yamada #define MPHY_DX_BDLR0 (0x007 << MPHY_SHIFT) 133fada9eafSMasahiro Yamada #define MPHY_DX_BDLR1 (0x008 << MPHY_SHIFT) 134fada9eafSMasahiro Yamada #define MPHY_DX_BDLR2 (0x009 << MPHY_SHIFT) 135fada9eafSMasahiro Yamada #define MPHY_DX_BDLR3 (0x00A << MPHY_SHIFT) 136fada9eafSMasahiro Yamada #define MPHY_DX_BDLR4 (0x00B << MPHY_SHIFT) 137fada9eafSMasahiro Yamada #define MPHY_DX_BDLR5 (0x00C << MPHY_SHIFT) 138fada9eafSMasahiro Yamada #define MPHY_DX_BDLR6 (0x00D << MPHY_SHIFT) 139fada9eafSMasahiro Yamada #define MPHY_DX_LCDLR0 (0x00E << MPHY_SHIFT) 140fada9eafSMasahiro Yamada #define MPHY_DX_LCDLR1 (0x00F << MPHY_SHIFT) 141fada9eafSMasahiro Yamada #define MPHY_DX_LCDLR2 (0x010 << MPHY_SHIFT) 142fada9eafSMasahiro Yamada #define MPHY_DX_MDLR (0x011 << MPHY_SHIFT) 143fada9eafSMasahiro Yamada #define MPHY_DX_GTR (0x012 << MPHY_SHIFT) 14415607d0dSMasahiro Yamada 145fada9eafSMasahiro Yamada #endif /* UNIPHIER_DDRMPHY_REGS_H */ 146