12c2ab3d4SMasahiro Yamada /* 2*4914a68dSMasahiro Yamada * Copyright (C) 2017 Socionext Inc. 3*4914a68dSMasahiro Yamada * 42c2ab3d4SMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 52c2ab3d4SMasahiro Yamada */ 62c2ab3d4SMasahiro Yamada 7*4914a68dSMasahiro Yamada #include <linux/delay.h> 8*4914a68dSMasahiro Yamada 91d21e1b9SMasahiro Yamada #include "../init.h" 10*4914a68dSMasahiro Yamada #include "../sc64-regs.h" 11*4914a68dSMasahiro Yamada #include "pll.h" 12*4914a68dSMasahiro Yamada 13*4914a68dSMasahiro Yamada /* PLL type: SSC */ 14*4914a68dSMasahiro Yamada #define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* CPU/ARM */ 15*4914a68dSMasahiro Yamada #define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* misc */ 16*4914a68dSMasahiro Yamada #define SC_SPLL2CTRL (SC_BASE_ADDR | 0x1420) /* DSP */ 17*4914a68dSMasahiro Yamada #define SC_VPPLLCTRL (SC_BASE_ADDR | 0x1430) /* VPE */ 18*4914a68dSMasahiro Yamada #define SC_VGPLLCTRL (SC_BASE_ADDR | 0x1440) 19*4914a68dSMasahiro Yamada #define SC_DECPLLCTRL (SC_BASE_ADDR | 0x1450) 20*4914a68dSMasahiro Yamada #define SC_ENCPLLCTRL (SC_BASE_ADDR | 0x1460) 21*4914a68dSMasahiro Yamada #define SC_PXFPLLCTRL (SC_BASE_ADDR | 0x1470) 22*4914a68dSMasahiro Yamada #define SC_DPLL0CTRL (SC_BASE_ADDR | 0x1480) /* DDR memory 0 */ 23*4914a68dSMasahiro Yamada #define SC_DPLL1CTRL (SC_BASE_ADDR | 0x1490) /* DDR memory 1 */ 24*4914a68dSMasahiro Yamada #define SC_DPLL2CTRL (SC_BASE_ADDR | 0x14a0) /* DDR memory 2 */ 25*4914a68dSMasahiro Yamada #define SC_VSPLLCTRL (SC_BASE_ADDR | 0x14c0) 26*4914a68dSMasahiro Yamada 27*4914a68dSMasahiro Yamada /* PLL type: VPLL27 */ 28*4914a68dSMasahiro Yamada #define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500) 29*4914a68dSMasahiro Yamada #define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520) 30*4914a68dSMasahiro Yamada 31*4914a68dSMasahiro Yamada /* PLL type: DSPLL */ 32*4914a68dSMasahiro Yamada #define SC_VPLL8KCTRL (SC_BASE_ADDR | 0x1540) 331d21e1b9SMasahiro Yamada 342c2ab3d4SMasahiro Yamada void uniphier_pxs3_pll_init(void) 352c2ab3d4SMasahiro Yamada { 36*4914a68dSMasahiro Yamada uniphier_ld20_sscpll_init(SC_CPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4); 37*4914a68dSMasahiro Yamada /* do nothing for SPLL */ 38*4914a68dSMasahiro Yamada uniphier_ld20_sscpll_init(SC_SPLL2CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4); 39*4914a68dSMasahiro Yamada uniphier_ld20_sscpll_init(SC_VPPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); 40*4914a68dSMasahiro Yamada uniphier_ld20_sscpll_init(SC_VGPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); 41*4914a68dSMasahiro Yamada uniphier_ld20_sscpll_init(SC_DECPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); 42*4914a68dSMasahiro Yamada uniphier_ld20_sscpll_init(SC_ENCPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4); 43*4914a68dSMasahiro Yamada uniphier_ld20_sscpll_init(SC_PXFPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); 44*4914a68dSMasahiro Yamada uniphier_ld20_sscpll_init(SC_VSPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); 45*4914a68dSMasahiro Yamada 46*4914a68dSMasahiro Yamada mdelay(1); 47*4914a68dSMasahiro Yamada 48*4914a68dSMasahiro Yamada uniphier_ld20_sscpll_ssc_en(SC_CPLLCTRL); 49*4914a68dSMasahiro Yamada uniphier_ld20_sscpll_ssc_en(SC_SPLL2CTRL); 50*4914a68dSMasahiro Yamada uniphier_ld20_sscpll_ssc_en(SC_VPPLLCTRL); 51*4914a68dSMasahiro Yamada uniphier_ld20_sscpll_ssc_en(SC_VGPLLCTRL); 52*4914a68dSMasahiro Yamada uniphier_ld20_sscpll_ssc_en(SC_DECPLLCTRL); 53*4914a68dSMasahiro Yamada uniphier_ld20_sscpll_ssc_en(SC_ENCPLLCTRL); 54*4914a68dSMasahiro Yamada uniphier_ld20_sscpll_ssc_en(SC_PXFPLLCTRL); 55*4914a68dSMasahiro Yamada uniphier_ld20_sscpll_ssc_en(SC_DPLL0CTRL); 56*4914a68dSMasahiro Yamada uniphier_ld20_sscpll_ssc_en(SC_DPLL1CTRL); 57*4914a68dSMasahiro Yamada uniphier_ld20_sscpll_ssc_en(SC_DPLL2CTRL); 58*4914a68dSMasahiro Yamada uniphier_ld20_sscpll_ssc_en(SC_VSPLLCTRL); 59*4914a68dSMasahiro Yamada 60*4914a68dSMasahiro Yamada uniphier_ld20_vpll27_init(SC_VPLL27FCTRL); 61*4914a68dSMasahiro Yamada uniphier_ld20_vpll27_init(SC_VPLL27ACTRL); 62*4914a68dSMasahiro Yamada 63*4914a68dSMasahiro Yamada uniphier_ld20_dspll_init(SC_VPLL8KCTRL); 642c2ab3d4SMasahiro Yamada } 65