16a3e4274SMasahiro Yamada /* 26a3e4274SMasahiro Yamada * Copyright (C) 2013-2014 Panasonic Corporation 36a3e4274SMasahiro Yamada * Copyright (C) 2015-2016 Socionext Inc. 46a3e4274SMasahiro Yamada * 56a3e4274SMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 66a3e4274SMasahiro Yamada */ 76a3e4274SMasahiro Yamada 8*d9a70368SMasahiro Yamada #include <linux/delay.h> 96a3e4274SMasahiro Yamada #include <linux/io.h> 106a3e4274SMasahiro Yamada 116a3e4274SMasahiro Yamada #include "../init.h" 126a3e4274SMasahiro Yamada #include "../sc-regs.h" 136a3e4274SMasahiro Yamada #include "../sg-regs.h" 146a3e4274SMasahiro Yamada #include "pll.h" 156a3e4274SMasahiro Yamada 166a3e4274SMasahiro Yamada static void upll_init(void) 176a3e4274SMasahiro Yamada { 186a3e4274SMasahiro Yamada u32 tmp, clk_mode_upll, clk_mode_axosel; 196a3e4274SMasahiro Yamada 206a3e4274SMasahiro Yamada tmp = readl(SG_PINMON0); 216a3e4274SMasahiro Yamada clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK; 226a3e4274SMasahiro Yamada clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; 236a3e4274SMasahiro Yamada 246a3e4274SMasahiro Yamada /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */ 256a3e4274SMasahiro Yamada tmp = readl(SC_UPLLCTRL); 266a3e4274SMasahiro Yamada tmp &= ~0x18000000; 276a3e4274SMasahiro Yamada writel(tmp, SC_UPLLCTRL); 286a3e4274SMasahiro Yamada 296a3e4274SMasahiro Yamada if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) { 306a3e4274SMasahiro Yamada if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U || 316a3e4274SMasahiro Yamada clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) { 326a3e4274SMasahiro Yamada /* AXO: 25MHz */ 336a3e4274SMasahiro Yamada tmp &= ~0x07ffffff; 346a3e4274SMasahiro Yamada tmp |= 0x0228f5c0; 356a3e4274SMasahiro Yamada } else { 366a3e4274SMasahiro Yamada /* AXO: default 24.576MHz */ 376a3e4274SMasahiro Yamada tmp &= ~0x07ffffff; 386a3e4274SMasahiro Yamada tmp |= 0x02328000; 396a3e4274SMasahiro Yamada } 406a3e4274SMasahiro Yamada } 416a3e4274SMasahiro Yamada 426a3e4274SMasahiro Yamada writel(tmp, SC_UPLLCTRL); 436a3e4274SMasahiro Yamada 446a3e4274SMasahiro Yamada /* set 1 to K_LD(UPLLCTRL.bit[27]) */ 456a3e4274SMasahiro Yamada tmp |= 0x08000000; 466a3e4274SMasahiro Yamada writel(tmp, SC_UPLLCTRL); 476a3e4274SMasahiro Yamada 486a3e4274SMasahiro Yamada /* wait 10 usec */ 496a3e4274SMasahiro Yamada udelay(10); 506a3e4274SMasahiro Yamada 516a3e4274SMasahiro Yamada /* set 1 to SNRT(UPLLCTRL.bit[28]) */ 526a3e4274SMasahiro Yamada tmp |= 0x10000000; 536a3e4274SMasahiro Yamada writel(tmp, SC_UPLLCTRL); 546a3e4274SMasahiro Yamada } 556a3e4274SMasahiro Yamada 566a3e4274SMasahiro Yamada static void vpll_init(void) 576a3e4274SMasahiro Yamada { 586a3e4274SMasahiro Yamada u32 tmp, clk_mode_axosel; 596a3e4274SMasahiro Yamada 606a3e4274SMasahiro Yamada tmp = readl(SG_PINMON0); 616a3e4274SMasahiro Yamada clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; 626a3e4274SMasahiro Yamada 636a3e4274SMasahiro Yamada /* set 1 to VPLA27WP and VPLA27WP */ 646a3e4274SMasahiro Yamada tmp = readl(SC_VPLL27ACTRL); 656a3e4274SMasahiro Yamada tmp |= 0x00000001; 666a3e4274SMasahiro Yamada writel(tmp, SC_VPLL27ACTRL); 676a3e4274SMasahiro Yamada tmp = readl(SC_VPLL27BCTRL); 686a3e4274SMasahiro Yamada tmp |= 0x00000001; 696a3e4274SMasahiro Yamada writel(tmp, SC_VPLL27BCTRL); 706a3e4274SMasahiro Yamada 716a3e4274SMasahiro Yamada /* Set 0 to VPLA_K_LD and VPLB_K_LD */ 726a3e4274SMasahiro Yamada tmp = readl(SC_VPLL27ACTRL3); 736a3e4274SMasahiro Yamada tmp &= ~0x10000000; 746a3e4274SMasahiro Yamada writel(tmp, SC_VPLL27ACTRL3); 756a3e4274SMasahiro Yamada tmp = readl(SC_VPLL27BCTRL3); 766a3e4274SMasahiro Yamada tmp &= ~0x10000000; 776a3e4274SMasahiro Yamada writel(tmp, SC_VPLL27BCTRL3); 786a3e4274SMasahiro Yamada 796a3e4274SMasahiro Yamada /* Set 0 to VPLA_SNRST and VPLB_SNRST */ 806a3e4274SMasahiro Yamada tmp = readl(SC_VPLL27ACTRL2); 816a3e4274SMasahiro Yamada tmp &= ~0x10000000; 826a3e4274SMasahiro Yamada writel(tmp, SC_VPLL27ACTRL2); 836a3e4274SMasahiro Yamada tmp = readl(SC_VPLL27BCTRL2); 846a3e4274SMasahiro Yamada tmp &= ~0x10000000; 856a3e4274SMasahiro Yamada writel(tmp, SC_VPLL27BCTRL2); 866a3e4274SMasahiro Yamada 876a3e4274SMasahiro Yamada /* Set 0x20 to VPLA_SNRST and VPLB_SNRST */ 886a3e4274SMasahiro Yamada tmp = readl(SC_VPLL27ACTRL2); 896a3e4274SMasahiro Yamada tmp &= ~0x0000007f; 906a3e4274SMasahiro Yamada tmp |= 0x00000020; 916a3e4274SMasahiro Yamada writel(tmp, SC_VPLL27ACTRL2); 926a3e4274SMasahiro Yamada tmp = readl(SC_VPLL27BCTRL2); 936a3e4274SMasahiro Yamada tmp &= ~0x0000007f; 946a3e4274SMasahiro Yamada tmp |= 0x00000020; 956a3e4274SMasahiro Yamada writel(tmp, SC_VPLL27BCTRL2); 966a3e4274SMasahiro Yamada 976a3e4274SMasahiro Yamada if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U || 986a3e4274SMasahiro Yamada clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) { 996a3e4274SMasahiro Yamada /* AXO: 25MHz */ 1006a3e4274SMasahiro Yamada tmp = readl(SC_VPLL27ACTRL3); 1016a3e4274SMasahiro Yamada tmp &= ~0x000fffff; 1026a3e4274SMasahiro Yamada tmp |= 0x00066664; 1036a3e4274SMasahiro Yamada writel(tmp, SC_VPLL27ACTRL3); 1046a3e4274SMasahiro Yamada tmp = readl(SC_VPLL27BCTRL3); 1056a3e4274SMasahiro Yamada tmp &= ~0x000fffff; 1066a3e4274SMasahiro Yamada tmp |= 0x00066664; 1076a3e4274SMasahiro Yamada writel(tmp, SC_VPLL27BCTRL3); 1086a3e4274SMasahiro Yamada } else { 1096a3e4274SMasahiro Yamada /* AXO: default 24.576MHz */ 1106a3e4274SMasahiro Yamada tmp = readl(SC_VPLL27ACTRL3); 1116a3e4274SMasahiro Yamada tmp &= ~0x000fffff; 1126a3e4274SMasahiro Yamada tmp |= 0x000f5800; 1136a3e4274SMasahiro Yamada writel(tmp, SC_VPLL27ACTRL3); 1146a3e4274SMasahiro Yamada tmp = readl(SC_VPLL27BCTRL3); 1156a3e4274SMasahiro Yamada tmp &= ~0x000fffff; 1166a3e4274SMasahiro Yamada tmp |= 0x000f5800; 1176a3e4274SMasahiro Yamada writel(tmp, SC_VPLL27BCTRL3); 1186a3e4274SMasahiro Yamada } 1196a3e4274SMasahiro Yamada 1206a3e4274SMasahiro Yamada /* Set 1 to VPLA_K_LD and VPLB_K_LD */ 1216a3e4274SMasahiro Yamada tmp = readl(SC_VPLL27ACTRL3); 1226a3e4274SMasahiro Yamada tmp |= 0x10000000; 1236a3e4274SMasahiro Yamada writel(tmp, SC_VPLL27ACTRL3); 1246a3e4274SMasahiro Yamada tmp = readl(SC_VPLL27BCTRL3); 1256a3e4274SMasahiro Yamada tmp |= 0x10000000; 1266a3e4274SMasahiro Yamada writel(tmp, SC_VPLL27BCTRL3); 1276a3e4274SMasahiro Yamada 1286a3e4274SMasahiro Yamada /* wait 10 usec */ 1296a3e4274SMasahiro Yamada udelay(10); 1306a3e4274SMasahiro Yamada 1316a3e4274SMasahiro Yamada /* Set 0 to VPLA_SNRST and VPLB_SNRST */ 1326a3e4274SMasahiro Yamada tmp = readl(SC_VPLL27ACTRL2); 1336a3e4274SMasahiro Yamada tmp |= 0x10000000; 1346a3e4274SMasahiro Yamada writel(tmp, SC_VPLL27ACTRL2); 1356a3e4274SMasahiro Yamada tmp = readl(SC_VPLL27BCTRL2); 1366a3e4274SMasahiro Yamada tmp |= 0x10000000; 1376a3e4274SMasahiro Yamada writel(tmp, SC_VPLL27BCTRL2); 1386a3e4274SMasahiro Yamada 1396a3e4274SMasahiro Yamada /* set 0 to VPLA27WP and VPLA27WP */ 1406a3e4274SMasahiro Yamada tmp = readl(SC_VPLL27ACTRL); 1416a3e4274SMasahiro Yamada tmp &= ~0x00000001; 1426a3e4274SMasahiro Yamada writel(tmp, SC_VPLL27ACTRL); 1436a3e4274SMasahiro Yamada tmp = readl(SC_VPLL27BCTRL); 1446a3e4274SMasahiro Yamada tmp |= ~0x00000001; 1456a3e4274SMasahiro Yamada writel(tmp, SC_VPLL27BCTRL); 1466a3e4274SMasahiro Yamada } 1476a3e4274SMasahiro Yamada 1486a3e4274SMasahiro Yamada void uniphier_ld4_pll_init(void) 1496a3e4274SMasahiro Yamada { 1506a3e4274SMasahiro Yamada upll_init(); 1516a3e4274SMasahiro Yamada vpll_init(); 1526a3e4274SMasahiro Yamada uniphier_ld4_dpll_ssc_en(); 1536a3e4274SMasahiro Yamada } 154