1 /*
2  * Copyright (C) 2013-2014 Panasonic Corporation
3  * Copyright (C) 2015-2016 Socionext Inc.
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 #include <common.h>
9 #include <linux/errno.h>
10 #include <linux/io.h>
11 
12 #include "../init.h"
13 #include "../sc-regs.h"
14 
15 #undef DPLL_SSC_RATE_1PER
16 
17 int uniphier_pro4_dpll_init(const struct uniphier_board_data *bd)
18 {
19 	unsigned int dram_freq = bd->dram_freq;
20 	u32 tmp;
21 
22 	/*
23 	 * Set Frequency
24 	 * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
25 	 * to FOUT ( DPLLCTRL.bit[29:20] )
26 	 */
27 	tmp = readl(SC_DPLLCTRL);
28 	tmp &= ~(0x000f0000);
29 	switch (dram_freq) {
30 	case 1333:
31 		tmp |= 0x000d0000;
32 		break;
33 	case 1600:
34 		tmp |= 0x000c0000;
35 		break;
36 	default:
37 		pr_err("Unsupported frequency");
38 		return -EINVAL;
39 	}
40 
41 	/*
42 	 * Set Moduration rate
43 	 * Set 0x0(1%)/0x1(2%) to SSC_RATE(DPLLCTRL.bit[15])
44 	 */
45 #if defined(DPLL_SSC_RATE_1PER)
46 	tmp &= ~0x00008000;
47 #else
48 	tmp |= 0x00008000;
49 #endif
50 	writel(tmp, SC_DPLLCTRL);
51 
52 	tmp = readl(SC_DPLLCTRL2);
53 	tmp |= SC_DPLLCTRL2_NRSTDS;
54 	writel(tmp, SC_DPLLCTRL2);
55 
56 	/* Wait until dpll gets stable */
57 	udelay(500);
58 
59 	return 0;
60 }
61