1*78c627cfSMasahiro Yamada /* 2*78c627cfSMasahiro Yamada * Copyright (C) 2015-2017 Socionext Inc. 3*78c627cfSMasahiro Yamada * 4*78c627cfSMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 5*78c627cfSMasahiro Yamada */ 6*78c627cfSMasahiro Yamada 7*78c627cfSMasahiro Yamada #include <linux/io.h> 8*78c627cfSMasahiro Yamada 9*78c627cfSMasahiro Yamada #include "../init.h" 10*78c627cfSMasahiro Yamada #include "../sc-regs.h" 11*78c627cfSMasahiro Yamada 12*78c627cfSMasahiro Yamada void uniphier_pro5_dram_clk_init(void) 13*78c627cfSMasahiro Yamada { 14*78c627cfSMasahiro Yamada u32 tmp; 15*78c627cfSMasahiro Yamada 16*78c627cfSMasahiro Yamada /* 17*78c627cfSMasahiro Yamada * deassert reset 18*78c627cfSMasahiro Yamada * UMCA2: Ch1 (DDR3) 19*78c627cfSMasahiro Yamada * UMCA1, UMC31: Ch0 (WIO1) 20*78c627cfSMasahiro Yamada * UMCA0, UMC30: Ch0 (WIO0) 21*78c627cfSMasahiro Yamada */ 22*78c627cfSMasahiro Yamada tmp = readl(SC_RSTCTRL4); 23*78c627cfSMasahiro Yamada tmp |= SC_RSTCTRL4_NRST_UMCSB | SC_RSTCTRL4_NRST_UMCA2 | 24*78c627cfSMasahiro Yamada SC_RSTCTRL4_NRST_UMCA1 | SC_RSTCTRL4_NRST_UMCA0 | 25*78c627cfSMasahiro Yamada SC_RSTCTRL4_NRST_UMC31 | SC_RSTCTRL4_NRST_UMC30; 26*78c627cfSMasahiro Yamada writel(tmp, SC_RSTCTRL4); 27*78c627cfSMasahiro Yamada readl(SC_RSTCTRL4); /* dummy read */ 28*78c627cfSMasahiro Yamada 29*78c627cfSMasahiro Yamada /* provide clocks */ 30*78c627cfSMasahiro Yamada tmp = readl(SC_CLKCTRL4); 31*78c627cfSMasahiro Yamada tmp |= SC_CLKCTRL4_CEN_UMCSB | SC_CLKCTRL4_CEN_UMC1 | 32*78c627cfSMasahiro Yamada SC_CLKCTRL4_CEN_UMC0; 33*78c627cfSMasahiro Yamada writel(tmp, SC_CLKCTRL4); 34*78c627cfSMasahiro Yamada readl(SC_CLKCTRL4); /* dummy read */ 35*78c627cfSMasahiro Yamada } 36