1 /* 2 * Copyright (C) 2012-2015 Panasonic Corporation 3 * Copyright (C) 2015-2016 Socionext Inc. 4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <libfdt.h> 11 #include <linux/io.h> 12 13 #include "init.h" 14 #include "micro-support-card.h" 15 #include "sg-regs.h" 16 #include "soc-info.h" 17 18 DECLARE_GLOBAL_DATA_PTR; 19 20 static void uniphier_setup_xirq(void) 21 { 22 const void *fdt = gd->fdt_blob; 23 int soc_node, aidet_node; 24 const fdt32_t *val; 25 unsigned long aidet_base; 26 u32 tmp; 27 28 soc_node = fdt_path_offset(fdt, "/soc"); 29 if (soc_node < 0) 30 return; 31 32 aidet_node = fdt_subnode_offset_namelen(fdt, soc_node, "aidet", 5); 33 if (aidet_node < 0) 34 return; 35 36 val = fdt_getprop(fdt, aidet_node, "reg", NULL); 37 if (!val) 38 return; 39 40 aidet_base = fdt32_to_cpu(*val); 41 42 tmp = readl(aidet_base + 8); /* AIDET DETCONFR2 */ 43 tmp |= 0x00ff0000; /* Set XIRQ0-7 low active */ 44 writel(tmp, aidet_base + 8); 45 46 tmp = readl(0x55000090); /* IRQCTL */ 47 tmp |= 0x000000ff; 48 writel(tmp, 0x55000090); 49 } 50 51 #ifdef CONFIG_ARCH_UNIPHIER_LD11 52 static void uniphier_ld11_misc_init(void) 53 { 54 sg_set_pinsel(149, 14, 8, 4); /* XIRQ0 -> XIRQ0 */ 55 sg_set_iectrl(149); 56 sg_set_pinsel(153, 14, 8, 4); /* XIRQ4 -> XIRQ4 */ 57 sg_set_iectrl(153); 58 } 59 #endif 60 61 #ifdef CONFIG_ARCH_UNIPHIER_LD20 62 static void uniphier_ld20_misc_init(void) 63 { 64 sg_set_pinsel(149, 14, 8, 4); /* XIRQ0 -> XIRQ0 */ 65 sg_set_iectrl(149); 66 sg_set_pinsel(153, 14, 8, 4); /* XIRQ4 -> XIRQ4 */ 67 sg_set_iectrl(153); 68 69 /* ES1 errata: increase VDD09 supply to suppress VBO noise */ 70 if (uniphier_get_soc_revision() == 1) { 71 writel(0x00000003, 0x6184e004); 72 writel(0x00000100, 0x6184e040); 73 writel(0x0000b500, 0x6184e024); 74 writel(0x00000001, 0x6184e000); 75 } 76 } 77 #endif 78 79 struct uniphier_initdata { 80 unsigned int soc_id; 81 bool nand_2cs; 82 void (*sbc_init)(void); 83 void (*pll_init)(void); 84 void (*clk_init)(void); 85 void (*misc_init)(void); 86 }; 87 88 static const struct uniphier_initdata uniphier_initdata[] = { 89 #if defined(CONFIG_ARCH_UNIPHIER_LD4) 90 { 91 .soc_id = UNIPHIER_LD4_ID, 92 .nand_2cs = true, 93 .sbc_init = uniphier_ld4_sbc_init, 94 .pll_init = uniphier_ld4_pll_init, 95 .clk_init = uniphier_ld4_clk_init, 96 }, 97 #endif 98 #if defined(CONFIG_ARCH_UNIPHIER_PRO4) 99 { 100 .soc_id = UNIPHIER_PRO4_ID, 101 .nand_2cs = false, 102 .sbc_init = uniphier_sbc_init_savepin, 103 .pll_init = uniphier_pro4_pll_init, 104 .clk_init = uniphier_pro4_clk_init, 105 }, 106 #endif 107 #if defined(CONFIG_ARCH_UNIPHIER_SLD8) 108 { 109 .soc_id = UNIPHIER_SLD8_ID, 110 .nand_2cs = true, 111 .sbc_init = uniphier_ld4_sbc_init, 112 .pll_init = uniphier_ld4_pll_init, 113 .clk_init = uniphier_ld4_clk_init, 114 }, 115 #endif 116 #if defined(CONFIG_ARCH_UNIPHIER_PRO5) 117 { 118 .soc_id = UNIPHIER_PRO5_ID, 119 .nand_2cs = true, 120 .sbc_init = uniphier_sbc_init_savepin, 121 .clk_init = uniphier_pro5_clk_init, 122 }, 123 #endif 124 #if defined(CONFIG_ARCH_UNIPHIER_PXS2) 125 { 126 .soc_id = UNIPHIER_PXS2_ID, 127 .nand_2cs = true, 128 .sbc_init = uniphier_pxs2_sbc_init, 129 .clk_init = uniphier_pxs2_clk_init, 130 }, 131 #endif 132 #if defined(CONFIG_ARCH_UNIPHIER_LD6B) 133 { 134 .soc_id = UNIPHIER_LD6B_ID, 135 .nand_2cs = true, 136 .sbc_init = uniphier_pxs2_sbc_init, 137 .clk_init = uniphier_pxs2_clk_init, 138 }, 139 #endif 140 #if defined(CONFIG_ARCH_UNIPHIER_LD11) 141 { 142 .soc_id = UNIPHIER_LD11_ID, 143 .nand_2cs = false, 144 .sbc_init = uniphier_ld11_sbc_init, 145 .pll_init = uniphier_ld11_pll_init, 146 .clk_init = uniphier_ld11_clk_init, 147 .misc_init = uniphier_ld11_misc_init, 148 }, 149 #endif 150 #if defined(CONFIG_ARCH_UNIPHIER_LD20) 151 { 152 .soc_id = UNIPHIER_LD20_ID, 153 .nand_2cs = false, 154 .sbc_init = uniphier_ld11_sbc_init, 155 .pll_init = uniphier_ld20_pll_init, 156 .clk_init = uniphier_ld20_clk_init, 157 .misc_init = uniphier_ld20_misc_init, 158 }, 159 #endif 160 #if defined(CONFIG_ARCH_UNIPHIER_PXS3) 161 { 162 .soc_id = UNIPHIER_PXS3_ID, 163 .nand_2cs = false, 164 .sbc_init = uniphier_pxs2_sbc_init, 165 .pll_init = uniphier_pxs3_pll_init, 166 .clk_init = uniphier_pxs3_clk_init, 167 }, 168 #endif 169 }; 170 UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_initdata, uniphier_initdata) 171 172 int board_init(void) 173 { 174 const struct uniphier_initdata *initdata; 175 int ret; 176 177 led_puts("U0"); 178 179 initdata = uniphier_get_initdata(); 180 if (!initdata) { 181 pr_err("unsupported SoC\n"); 182 return -EINVAL; 183 } 184 185 initdata->sbc_init(); 186 187 support_card_init(); 188 189 led_puts("U0"); 190 191 if (IS_ENABLED(CONFIG_NAND_DENALI)) { 192 ret = uniphier_pin_init(initdata->nand_2cs ? 193 "nand2cs_grp" : "nand_grp"); 194 if (ret) 195 pr_err("failed to init NAND pins\n"); 196 } 197 198 led_puts("U1"); 199 200 if (initdata->pll_init) 201 initdata->pll_init(); 202 203 led_puts("U2"); 204 205 if (initdata->clk_init) 206 initdata->clk_init(); 207 208 led_puts("U3"); 209 210 if (initdata->misc_init) 211 initdata->misc_init(); 212 213 led_puts("U4"); 214 215 uniphier_setup_xirq(); 216 217 led_puts("U5"); 218 219 support_card_late_init(); 220 221 led_puts("Uboo"); 222 223 return 0; 224 } 225