xref: /openbmc/u-boot/arch/arm/mach-uniphier/arm32/psci_smp.S (revision 00caae6d)
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1/*
2 * Copyright (C) 2016 Socionext Inc.
3 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
4 *
5 * SPDX-License-Identifier:	GPL-2.0+
6 */
7
8#include <linux/linkage.h>
9#include <asm/system.h>
10
11	.section ._secure.text, "ax"
12
13ENTRY(uniphier_smp_trampoline)
14	ldr	r0, 0f
15	mrc	p15, 0, r1, c1, c0, 0	@ SCTLR (System Control Register)
16	orr	r1, r1, #CR_I		@ Enable ICache
17	bic	r1, r1, #(CR_C | CR_M)	@ Disable MMU and Dcache
18	mcr	p15, 0, r1, c1, c0, 0
19
20	bx	r0
210:	.word	uniphier_secondary_startup
22	.globl	uniphier_smp_trampoline_end
23uniphier_smp_trampoline_end:
24ENDPROC(uniphier_smp_trampoline)
25
26LENTRY(uniphier_secondary_startup)
27	mrc	p15, 0, r1, c0, c0, 5	@ MPIDR (Multiprocessor Affinity Reg)
28	and	r1, r1, #0xff
29
30	ldr	r2, =uniphier_smp_booted
31	mov	r0, #1
32	str	r0, [r2, r1, lsl #2]
33
34	ldr	r2, =uniphier_psci_holding_pen_release
35pen:	ldr	r0, [r2]
36	cmp	r0, r1
37	beq	psci_cpu_entry
38	wfe
39	b	pen
40ENDPROC(uniphier_secondary_startup)
41

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