1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2016 Socionext Inc.
4  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5  */
6 
7 #include <common.h>
8 #include <linux/bitops.h>
9 #include <linux/delay.h>
10 #include <linux/io.h>
11 #include <linux/kernel.h>
12 #include <linux/printk.h>
13 #include <linux/psci.h>
14 #include <linux/sizes.h>
15 #include <asm/processor.h>
16 #include <asm/psci.h>
17 #include <asm/secure.h>
18 
19 #include "../debug.h"
20 #include "../soc-info.h"
21 #include "arm-mpcore.h"
22 #include "cache-uniphier.h"
23 
24 #define UNIPHIER_SMPCTRL_ROM_RSV2	0x59801208
25 
26 void uniphier_smp_trampoline(void);
27 void uniphier_smp_trampoline_end(void);
28 u32 uniphier_smp_booted[CONFIG_ARMV7_PSCI_NR_CPUS];
29 
30 static int uniphier_get_nr_cpus(void)
31 {
32 	switch (uniphier_get_soc_id()) {
33 	case UNIPHIER_PRO4_ID:
34 	case UNIPHIER_PRO5_ID:
35 		return 2;
36 	case UNIPHIER_PXS2_ID:
37 	case UNIPHIER_LD6B_ID:
38 		return 4;
39 	default:
40 		return 1;
41 	}
42 }
43 
44 static void uniphier_smp_kick_all_cpus(void)
45 {
46 	const u32 target_ways = BIT(0);
47 	size_t trmp_size;
48 	u32 trmp_src = (unsigned long)uniphier_smp_trampoline;
49 	u32 trmp_src_end = (unsigned long)uniphier_smp_trampoline_end;
50 	u32 trmp_dest, trmp_dest_end;
51 	int nr_cpus, i;
52 	int timeout = 1000;
53 
54 	nr_cpus = uniphier_get_nr_cpus();
55 	if (nr_cpus == 1)
56 		return;
57 
58 	for (i = 0; i < nr_cpus; i++)	/* lock ways for all CPUs */
59 		uniphier_cache_set_active_ways(i, 0);
60 	uniphier_cache_inv_way(target_ways);
61 	uniphier_cache_enable();
62 
63 	/* copy trampoline code */
64 	uniphier_cache_prefetch_range(trmp_src, trmp_src_end, target_ways);
65 
66 	trmp_size = trmp_src_end - trmp_src;
67 
68 	trmp_dest = trmp_src & (SZ_64K - 1);
69 	trmp_dest += SZ_1M - SZ_64K * 2;
70 
71 	trmp_dest_end = trmp_dest + trmp_size;
72 
73 	uniphier_cache_touch_range(trmp_dest, trmp_dest_end, target_ways);
74 
75 	writel(trmp_dest, UNIPHIER_SMPCTRL_ROM_RSV2);
76 
77 	asm("dsb	ishst\n" /* Ensure the write to ROM_RSV2 is visible */
78 	    "sev"); /* Bring up all secondary CPUs from Boot ROM into U-Boot */
79 
80 	while (--timeout) {
81 		int all_booted = 1;
82 
83 		for (i = 1; i < nr_cpus; i++)
84 			if (!uniphier_smp_booted[i])
85 				all_booted = 0;
86 		if (all_booted)
87 			break;
88 		udelay(1);
89 
90 		/* barrier here because uniphier_smp_booted[] may be updated */
91 		cpu_relax();
92 	}
93 
94 	if (!timeout)
95 		pr_warn("warning: some of secondary CPUs may not boot\n");
96 
97 	uniphier_cache_disable();
98 }
99 
100 void psci_board_init(void)
101 {
102 	unsigned long scu_base;
103 	u32 scu_ctrl, tmp;
104 
105 	asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (scu_base));
106 
107 	scu_ctrl = readl(scu_base + 0x30);
108 	if (!(scu_ctrl & 1))
109 		writel(scu_ctrl | 0x1, scu_base + 0x30);
110 
111 	scu_ctrl = readl(scu_base + SCU_CTRL);
112 	scu_ctrl |= SCU_ENABLE | SCU_STANDBY_ENABLE;
113 	writel(scu_ctrl, scu_base + SCU_CTRL);
114 
115 	tmp = readl(scu_base + SCU_SNSAC);
116 	tmp |= 0xfff;
117 	writel(tmp, scu_base + SCU_SNSAC);
118 
119 	uniphier_smp_kick_all_cpus();
120 }
121 
122 void psci_arch_init(void)
123 {
124 	u32 actlr;
125 
126 	asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (actlr));
127 	actlr |= 0x41;		/* set SMP and FW bits */
128 	asm("mcr p15, 0, %0, c1, c0, 1" : : "r" (actlr));
129 }
130 
131 u32 uniphier_psci_holding_pen_release __secure_data = 0xffffffff;
132 
133 int __secure psci_cpu_on(u32 function_id, u32 cpuid, u32 entry_point,
134 			 u32 context_id)
135 {
136 	u32 cpu = cpuid & 0xff;
137 
138 	debug_puts("[U-Boot PSCI]  psci_cpu_on: cpuid=");
139 	debug_puth(cpuid);
140 	debug_puts(", entry_point=");
141 	debug_puth(entry_point);
142 	debug_puts(", context_id=");
143 	debug_puth(context_id);
144 	debug_puts("\n");
145 
146 	psci_save(cpu, entry_point, context_id);
147 
148 	/* We assume D-cache is off, so do not call flush_dcache() here */
149 	uniphier_psci_holding_pen_release = cpu;
150 
151 	/* Send an event to wake up the secondary CPU. */
152 	asm("dsb	ishst\n"
153 	    "sev");
154 
155 	return PSCI_RET_SUCCESS;
156 }
157 
158 void __secure psci_system_reset(u32 function_id)
159 {
160 	reset_cpu(0);
161 }
162