1 /*
2  * Copyright (C) 2016 Socionext Inc.
3  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 #include <common.h>
9 #include <linux/bitops.h>
10 #include <linux/io.h>
11 #include <linux/kernel.h>
12 #include <linux/psci.h>
13 #include <linux/sizes.h>
14 #include <asm/processor.h>
15 #include <asm/psci.h>
16 #include <asm/secure.h>
17 
18 #include "../debug.h"
19 #include "../soc-info.h"
20 #include "arm-mpcore.h"
21 #include "cache-uniphier.h"
22 
23 #define UNIPHIER_SMPCTRL_ROM_RSV2	0x59801208
24 
25 void uniphier_smp_trampoline(void);
26 void uniphier_smp_trampoline_end(void);
27 u32 uniphier_smp_booted[CONFIG_ARMV7_PSCI_NR_CPUS];
28 
29 static int uniphier_get_nr_cpus(void)
30 {
31 	switch (uniphier_get_soc_id()) {
32 	case UNIPHIER_PRO4_ID:
33 	case UNIPHIER_PRO5_ID:
34 		return 2;
35 	case UNIPHIER_PXS2_ID:
36 	case UNIPHIER_LD6B_ID:
37 		return 4;
38 	default:
39 		return 1;
40 	}
41 }
42 
43 static void uniphier_smp_kick_all_cpus(void)
44 {
45 	const u32 target_ways = BIT(0);
46 	size_t trmp_size;
47 	u32 trmp_src = (unsigned long)uniphier_smp_trampoline;
48 	u32 trmp_src_end = (unsigned long)uniphier_smp_trampoline_end;
49 	u32 trmp_dest, trmp_dest_end;
50 	int nr_cpus, i;
51 	int timeout = 1000;
52 
53 	nr_cpus = uniphier_get_nr_cpus();
54 	if (nr_cpus == 1)
55 		return;
56 
57 	for (i = 0; i < nr_cpus; i++)	/* lock ways for all CPUs */
58 		uniphier_cache_set_active_ways(i, 0);
59 	uniphier_cache_inv_way(target_ways);
60 	uniphier_cache_enable();
61 
62 	/* copy trampoline code */
63 	uniphier_cache_prefetch_range(trmp_src, trmp_src_end, target_ways);
64 
65 	trmp_size = trmp_src_end - trmp_src;
66 
67 	trmp_dest = trmp_src & (SZ_64K - 1);
68 	trmp_dest += SZ_1M - SZ_64K * 2;
69 
70 	trmp_dest_end = trmp_dest + trmp_size;
71 
72 	uniphier_cache_touch_range(trmp_dest, trmp_dest_end, target_ways);
73 
74 	writel(trmp_dest, UNIPHIER_SMPCTRL_ROM_RSV2);
75 
76 	asm("dsb	ishst\n" /* Ensure the write to ROM_RSV2 is visible */
77 	    "sev"); /* Bring up all secondary CPUs from Boot ROM into U-Boot */
78 
79 	while (--timeout) {
80 		int all_booted = 1;
81 
82 		for (i = 1; i < nr_cpus; i++)
83 			if (!uniphier_smp_booted[i])
84 				all_booted = 0;
85 		if (all_booted)
86 			break;
87 		udelay(1);
88 
89 		/* barrier here because uniphier_smp_booted[] may be updated */
90 		cpu_relax();
91 	}
92 
93 	if (!timeout)
94 		printf("warning: some of secondary CPUs may not boot\n");
95 
96 	uniphier_cache_disable();
97 }
98 
99 void psci_board_init(void)
100 {
101 	unsigned long scu_base;
102 	u32 scu_ctrl, tmp;
103 
104 	asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (scu_base));
105 
106 	scu_ctrl = readl(scu_base + 0x30);
107 	if (!(scu_ctrl & 1))
108 		writel(scu_ctrl | 0x1, scu_base + 0x30);
109 
110 	scu_ctrl = readl(scu_base + SCU_CTRL);
111 	scu_ctrl |= SCU_ENABLE | SCU_STANDBY_ENABLE;
112 	writel(scu_ctrl, scu_base + SCU_CTRL);
113 
114 	tmp = readl(scu_base + SCU_SNSAC);
115 	tmp |= 0xfff;
116 	writel(tmp, scu_base + SCU_SNSAC);
117 
118 	uniphier_smp_kick_all_cpus();
119 }
120 
121 void psci_arch_init(void)
122 {
123 	u32 actlr;
124 
125 	asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (actlr));
126 	actlr |= 0x41;		/* set SMP and FW bits */
127 	asm("mcr p15, 0, %0, c1, c0, 1" : : "r" (actlr));
128 }
129 
130 u32 uniphier_psci_holding_pen_release __secure_data = 0xffffffff;
131 
132 int __secure psci_cpu_on(u32 function_id, u32 cpuid, u32 entry_point)
133 {
134 	u32 cpu = cpuid & 0xff;
135 
136 	debug_puts("[U-Boot PSCI]  psci_cpu_on: cpuid=");
137 	debug_puth(cpuid);
138 	debug_puts(", entry_point=");
139 	debug_puth(entry_point);
140 	debug_puts("\n");
141 
142 	psci_save_target_pc(cpu, entry_point);
143 
144 	/* We assume D-cache is off, so do not call flush_dcache() here */
145 	uniphier_psci_holding_pen_release = cpu;
146 
147 	/* Send an event to wake up the secondary CPU. */
148 	asm("dsb	ishst\n"
149 	    "sev");
150 
151 	return PSCI_RET_SUCCESS;
152 }
153 
154 void __secure psci_system_reset(u32 function_id)
155 {
156 	reset_cpu(0);
157 }
158