1e8a92932SMasahiro Yamada /* 2e8a92932SMasahiro Yamada * Copyright (C) 2016 Socionext Inc. 3e8a92932SMasahiro Yamada * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 4e8a92932SMasahiro Yamada * 5e8a92932SMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 6e8a92932SMasahiro Yamada */ 7e8a92932SMasahiro Yamada 8e8a92932SMasahiro Yamada #include <common.h> 9e8a92932SMasahiro Yamada #include <linux/bitops.h> 10e8a92932SMasahiro Yamada #include <linux/io.h> 11e8a92932SMasahiro Yamada #include <linux/kernel.h> 12e8a92932SMasahiro Yamada #include <linux/psci.h> 13e8a92932SMasahiro Yamada #include <linux/sizes.h> 14e8a92932SMasahiro Yamada #include <asm/processor.h> 15e8a92932SMasahiro Yamada #include <asm/psci.h> 16e8a92932SMasahiro Yamada #include <asm/secure.h> 17e8a92932SMasahiro Yamada 18e8a92932SMasahiro Yamada #include "../debug.h" 19e8a92932SMasahiro Yamada #include "../soc-info.h" 20e8a92932SMasahiro Yamada #include "arm-mpcore.h" 21e8a92932SMasahiro Yamada #include "cache-uniphier.h" 22e8a92932SMasahiro Yamada 23e8a92932SMasahiro Yamada #define UNIPHIER_SMPCTRL_ROM_RSV2 0x59801208 24e8a92932SMasahiro Yamada 25e8a92932SMasahiro Yamada void uniphier_smp_trampoline(void); 26e8a92932SMasahiro Yamada void uniphier_smp_trampoline_end(void); 27e8a92932SMasahiro Yamada u32 uniphier_smp_booted[CONFIG_ARMV7_PSCI_NR_CPUS]; 28e8a92932SMasahiro Yamada 29e8a92932SMasahiro Yamada static int uniphier_get_nr_cpus(void) 30e8a92932SMasahiro Yamada { 31e8a92932SMasahiro Yamada switch (uniphier_get_soc_type()) { 32e8a92932SMasahiro Yamada case SOC_UNIPHIER_SLD3: 33e8a92932SMasahiro Yamada case SOC_UNIPHIER_PRO4: 34e8a92932SMasahiro Yamada case SOC_UNIPHIER_PRO5: 35e8a92932SMasahiro Yamada return 2; 36e8a92932SMasahiro Yamada case SOC_UNIPHIER_PXS2: 37e8a92932SMasahiro Yamada case SOC_UNIPHIER_LD6B: 38e8a92932SMasahiro Yamada return 4; 39e8a92932SMasahiro Yamada default: 40e8a92932SMasahiro Yamada return 1; 41e8a92932SMasahiro Yamada } 42e8a92932SMasahiro Yamada } 43e8a92932SMasahiro Yamada 44e8a92932SMasahiro Yamada static void uniphier_smp_kick_all_cpus(void) 45e8a92932SMasahiro Yamada { 46e8a92932SMasahiro Yamada const u32 target_ways = BIT(0); 47e8a92932SMasahiro Yamada size_t trmp_size; 48e8a92932SMasahiro Yamada u32 trmp_src = (unsigned long)uniphier_smp_trampoline; 49e8a92932SMasahiro Yamada u32 trmp_src_end = (unsigned long)uniphier_smp_trampoline_end; 50e8a92932SMasahiro Yamada u32 trmp_dest, trmp_dest_end; 51e8a92932SMasahiro Yamada int nr_cpus, i; 52e8a92932SMasahiro Yamada int timeout = 1000; 53e8a92932SMasahiro Yamada 54e8a92932SMasahiro Yamada nr_cpus = uniphier_get_nr_cpus(); 55e8a92932SMasahiro Yamada if (nr_cpus == 1) 56e8a92932SMasahiro Yamada return; 57e8a92932SMasahiro Yamada 58e8a92932SMasahiro Yamada for (i = 0; i < nr_cpus; i++) /* lock ways for all CPUs */ 59e8a92932SMasahiro Yamada uniphier_cache_set_active_ways(i, 0); 60e8a92932SMasahiro Yamada uniphier_cache_inv_way(target_ways); 61e8a92932SMasahiro Yamada uniphier_cache_enable(); 62e8a92932SMasahiro Yamada 63e8a92932SMasahiro Yamada /* copy trampoline code */ 64e8a92932SMasahiro Yamada uniphier_cache_prefetch_range(trmp_src, trmp_src_end, target_ways); 65e8a92932SMasahiro Yamada 66e8a92932SMasahiro Yamada trmp_size = trmp_src_end - trmp_src; 67e8a92932SMasahiro Yamada 68e8a92932SMasahiro Yamada trmp_dest = trmp_src & (SZ_64K - 1); 69e8a92932SMasahiro Yamada trmp_dest += SZ_1M - SZ_64K * 2; 70e8a92932SMasahiro Yamada 71e8a92932SMasahiro Yamada trmp_dest_end = trmp_dest + trmp_size; 72e8a92932SMasahiro Yamada 73e8a92932SMasahiro Yamada uniphier_cache_touch_range(trmp_dest, trmp_dest_end, target_ways); 74e8a92932SMasahiro Yamada 75e8a92932SMasahiro Yamada writel(trmp_dest, UNIPHIER_SMPCTRL_ROM_RSV2); 76e8a92932SMasahiro Yamada 77e8a92932SMasahiro Yamada asm("dsb ishst\n" /* Ensure the write to ROM_RSV2 is visible */ 78e8a92932SMasahiro Yamada "sev"); /* Bring up all secondary CPUs from Boot ROM into U-Boot */ 79e8a92932SMasahiro Yamada 80e8a92932SMasahiro Yamada while (--timeout) { 81e8a92932SMasahiro Yamada int all_booted = 1; 82e8a92932SMasahiro Yamada 83e8a92932SMasahiro Yamada for (i = 1; i < nr_cpus; i++) 84e8a92932SMasahiro Yamada if (!uniphier_smp_booted[i]) 85e8a92932SMasahiro Yamada all_booted = 0; 86e8a92932SMasahiro Yamada if (all_booted) 87e8a92932SMasahiro Yamada break; 88e8a92932SMasahiro Yamada udelay(1); 89e8a92932SMasahiro Yamada 90e8a92932SMasahiro Yamada /* barrier here because uniphier_smp_booted[] may be updated */ 91e8a92932SMasahiro Yamada cpu_relax(); 92e8a92932SMasahiro Yamada } 93e8a92932SMasahiro Yamada 94e8a92932SMasahiro Yamada if (!timeout) 95e8a92932SMasahiro Yamada printf("warning: some of secondary CPUs may not boot\n"); 96e8a92932SMasahiro Yamada 97e8a92932SMasahiro Yamada uniphier_cache_disable(); 98e8a92932SMasahiro Yamada } 99e8a92932SMasahiro Yamada 100e8a92932SMasahiro Yamada void psci_board_init(void) 101e8a92932SMasahiro Yamada { 102e8a92932SMasahiro Yamada unsigned long scu_base; 103e8a92932SMasahiro Yamada u32 scu_ctrl, tmp; 104e8a92932SMasahiro Yamada 105e8a92932SMasahiro Yamada asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (scu_base)); 106e8a92932SMasahiro Yamada 107e8a92932SMasahiro Yamada scu_ctrl = readl(scu_base + 0x30); 108e8a92932SMasahiro Yamada if (!(scu_ctrl & 1)) 109e8a92932SMasahiro Yamada writel(scu_ctrl | 0x1, scu_base + 0x30); 110e8a92932SMasahiro Yamada 111e8a92932SMasahiro Yamada scu_ctrl = readl(scu_base + SCU_CTRL); 112e8a92932SMasahiro Yamada scu_ctrl |= SCU_ENABLE | SCU_STANDBY_ENABLE; 113e8a92932SMasahiro Yamada writel(scu_ctrl, scu_base + SCU_CTRL); 114e8a92932SMasahiro Yamada 115e8a92932SMasahiro Yamada tmp = readl(scu_base + SCU_SNSAC); 116e8a92932SMasahiro Yamada tmp |= 0xfff; 117e8a92932SMasahiro Yamada writel(tmp, scu_base + SCU_SNSAC); 118e8a92932SMasahiro Yamada 119e8a92932SMasahiro Yamada uniphier_smp_kick_all_cpus(); 120e8a92932SMasahiro Yamada } 121e8a92932SMasahiro Yamada 122e8a92932SMasahiro Yamada void psci_arch_init(void) 123e8a92932SMasahiro Yamada { 124e8a92932SMasahiro Yamada u32 actlr; 125e8a92932SMasahiro Yamada 126e8a92932SMasahiro Yamada asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (actlr)); 127e8a92932SMasahiro Yamada actlr |= 0x41; /* set SMP and FW bits */ 128e8a92932SMasahiro Yamada asm("mcr p15, 0, %0, c1, c0, 1" : : "r" (actlr)); 129e8a92932SMasahiro Yamada } 130e8a92932SMasahiro Yamada 131e8a92932SMasahiro Yamada u32 uniphier_psci_holding_pen_release __secure_data = 0xffffffff; 132e8a92932SMasahiro Yamada 133e8a92932SMasahiro Yamada int __secure psci_cpu_on(u32 function_id, u32 cpuid, u32 entry_point) 134e8a92932SMasahiro Yamada { 135e8a92932SMasahiro Yamada u32 cpu = cpuid & 0xff; 136e8a92932SMasahiro Yamada 137e8a92932SMasahiro Yamada debug_puts("[U-Boot PSCI] psci_cpu_on: cpuid="); 138e8a92932SMasahiro Yamada debug_puth(cpuid); 139e8a92932SMasahiro Yamada debug_puts(", entry_point="); 140e8a92932SMasahiro Yamada debug_puth(entry_point); 141e8a92932SMasahiro Yamada debug_puts("\n"); 142e8a92932SMasahiro Yamada 143e8a92932SMasahiro Yamada psci_save_target_pc(cpu, entry_point); 144e8a92932SMasahiro Yamada 145e8a92932SMasahiro Yamada /* We assume D-cache is off, so do not call flush_dcache() here */ 146e8a92932SMasahiro Yamada uniphier_psci_holding_pen_release = cpu; 147e8a92932SMasahiro Yamada 148e8a92932SMasahiro Yamada /* Send an event to wake up the secondary CPU. */ 149e8a92932SMasahiro Yamada asm("dsb ishst\n" 150e8a92932SMasahiro Yamada "sev"); 151e8a92932SMasahiro Yamada 152e8a92932SMasahiro Yamada return PSCI_RET_SUCCESS; 153e8a92932SMasahiro Yamada } 154*928f3248SMasahiro Yamada 155*928f3248SMasahiro Yamada void __secure psci_system_reset(u32 function_id) 156*928f3248SMasahiro Yamada { 157*928f3248SMasahiro Yamada reset_cpu(0); 158*928f3248SMasahiro Yamada } 159