1/*
2 * Copyright (C) 2012-2015 Panasonic Corporation
3 * Copyright (C) 2015-2016 Socionext Inc.
4 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5 *
6 * SPDX-License-Identifier:	GPL-2.0+
7 */
8
9#include <config.h>
10#include <linux/linkage.h>
11#include <linux/sizes.h>
12#include <asm/system.h>
13
14ENTRY(lowlevel_init)
15	mov	r8, lr			@ persevere link reg across call
16
17	/*
18	 * The UniPhier Boot ROM loads SPL code to the L2 cache.
19	 * But CPUs can only do instruction fetch now because start.S has
20	 * cleared C and M bits.
21	 * First we need to turn on MMU and Dcache again to get back
22	 * data access to L2.
23	 */
24	mrc	p15, 0, r0, c1, c0, 0	@ SCTLR (System Control Register)
25	orr	r0, r0, #(CR_C | CR_M)	@ enable MMU and Dcache
26	mcr	p15, 0, r0, c1, c0, 0
27
28#ifdef CONFIG_DEBUG_LL
29	bl	debug_ll_init
30#endif
31
32	bl	setup_init_ram		@ RAM area for stack and page table
33
34	/*
35	 * Now we are using the page table embedded in the Boot ROM.
36	 * What we need to do next is to create a page table and switch
37	 * over to it.
38	 */
39	bl	create_page_table
40	bl	__v7_flush_dcache_all
41
42	/* Disable MMU and Dcache before switching Page Table */
43	mrc	p15, 0, r0, c1, c0, 0	@ SCTLR (System Control Register)
44	bic	r0, r0, #(CR_C | CR_M)	@ disable MMU and Dcache
45	mcr	p15, 0, r0, c1, c0, 0
46
47	bl	enable_mmu
48
49	mov	lr, r8			@ restore link
50	mov	pc, lr			@ back to my caller
51ENDPROC(lowlevel_init)
52
53ENTRY(enable_mmu)
54	mrc	p15, 0, r0, c2, c0, 2	@ TTBCR (Translation Table Base Control Register)
55	bic	r0, r0, #0x37
56	orr	r0, r0, #0x20		@ disable TTBR1
57	mcr	p15, 0, r0, c2, c0, 2
58
59	orr	r0, r12, #0x8		@ Outer Cacheability for table walks: WBWA
60	mcr	p15, 0, r0, c2, c0, 0   @ TTBR0
61
62	mov	r0, #0
63	mcr	p15, 0, r0, c8, c7, 0	@ invalidate TLBs
64
65	mov	r0, #-1			@ manager for all domains (No permission check)
66	mcr	p15, 0, r0, c3, c0, 0   @ DACR (Domain Access Control Register)
67
68	dsb
69	isb
70	/*
71	 * MMU on:
72	 * TLBs was already invalidated in "../start.S"
73	 * So, we don't need to invalidate it here.
74	 */
75	mrc	p15, 0, r0, c1, c0, 0	@ SCTLR (System Control Register)
76	orr	r0, r0, #(CR_C | CR_M)	@ MMU and Dcache enable
77	mcr	p15, 0, r0, c1, c0, 0
78
79	mov	pc, lr
80ENDPROC(enable_mmu)
81
82/*
83 * For PH1-Pro4 or older SoCs, the size of WAY is 32KB.
84 * It is large enough for tmp RAM.
85 */
86#define BOOT_RAM_SIZE	(SZ_32K)
87#define BOOT_RAM_BASE	((CONFIG_SPL_STACK) - (BOOT_RAM_SIZE))
88#define BOOT_RAM_WAYS	(0x00000100)	@ way 8
89
90#define SSCO_BASE		0x506c0000
91#define SSCOPE			0x244
92#define SSCOQM			0x248
93#define SSCOQAD			0x24c
94#define SSCOQSZ			0x250
95#define SSCOQWN			0x258
96#define SSCOPPQSEF		0x25c
97#define SSCOLPQS		0x260
98
99ENTRY(setup_init_ram)
100	ldr	r1, = SSCO_BASE
101
102	/* Touch to zero for the boot way */
1030:	ldr	r0, = 0x00408006	@ touch to zero with address range
104	str	r0, [r1, #SSCOQM]
105	ldr	r0, = BOOT_RAM_BASE
106	str	r0, [r1, #SSCOQAD]
107	ldr	r0, = BOOT_RAM_SIZE
108	str	r0, [r1, #SSCOQSZ]
109	ldr	r0, = BOOT_RAM_WAYS
110	str	r0, [r1, #SSCOQWN]
111	ldr	r0, [r1, #SSCOPPQSEF]
112	cmp	r0, #0			@ check if the command is successfully set
113	bne	0b			@ try again if an error occurs
114
1151:	ldr	r0, [r1, #SSCOLPQS]
116	cmp	r0, #0x4
117	bne	1b			@ wait until the operation is completed
118	str	r0, [r1, #SSCOLPQS]	@ clear the complete notification flag
119
120	mov	pc, lr
121ENDPROC(setup_init_ram)
122
123#define DEVICE	0x00002002 /* Non-shareable Device */
124#define NORMAL	0x0000000e /* Normal Memory Write-Back, No Write-Allocate */
125
126ENTRY(create_page_table)
127	ldr	r0, = DEVICE
128	ldr	r1, = BOOT_RAM_BASE
129	mov	r12, r1			@ r12 is preserved during D-cache flush
1300:	str	r0, [r1], #4		@ specify all the sections as Device
131	adds	r0, r0, #0x00100000
132	bcc	0b
133
134	ldr	r0, = NORMAL
135	str	r0, [r12]		@ mark the first section as Normal
136	add	r0, r0, #0x00100000
137	str	r0, [r12, #4]		@ mark the second section as Normal
138	mov	pc, lr
139ENDPROC(create_page_table)
140