1/*
2 * Copyright (C) 2012-2015 Panasonic Corporation
3 * Copyright (C) 2015-2016 Socionext Inc.
4 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5 *
6 * SPDX-License-Identifier:	GPL-2.0+
7 */
8
9#include <config.h>
10#include <linux/linkage.h>
11#include <linux/sizes.h>
12#include <asm/system.h>
13
14#include "ssc-regs.h"
15
16ENTRY(lowlevel_init)
17	mov	r8, lr			@ persevere link reg across call
18
19	/*
20	 * The UniPhier Boot ROM loads SPL code to the L2 cache.
21	 * But CPUs can only do instruction fetch now because start.S has
22	 * cleared C and M bits.
23	 * First we need to turn on MMU and Dcache again to get back
24	 * data access to L2.
25	 */
26	mrc	p15, 0, r0, c1, c0, 0	@ SCTLR (System Control Register)
27	orr	r0, r0, #(CR_C | CR_M)	@ enable MMU and Dcache
28	mcr	p15, 0, r0, c1, c0, 0
29
30#ifdef CONFIG_DEBUG_LL
31	bl	debug_ll_init
32#endif
33
34	bl	setup_init_ram		@ RAM area for stack and page table
35
36	/*
37	 * Now we are using the page table embedded in the Boot ROM.
38	 * It is not handy since it is not a straight mapped table for sLD3.
39	 * Also, the access to the external bus is prohibited.  What we need
40	 * to do next is to create a page table and switch over to it.
41	 */
42	bl	create_page_table
43	bl	__v7_flush_dcache_all
44
45	/* Disable MMU and Dcache before switching Page Table */
46	mrc	p15, 0, r0, c1, c0, 0	@ SCTLR (System Control Register)
47	bic	r0, r0, #(CR_C | CR_M)	@ disable MMU and Dcache
48	mcr	p15, 0, r0, c1, c0, 0
49
50	bl	enable_mmu
51
52	mov	lr, r8			@ restore link
53	mov	pc, lr			@ back to my caller
54ENDPROC(lowlevel_init)
55
56ENTRY(enable_mmu)
57	mrc	p15, 0, r0, c2, c0, 2	@ TTBCR (Translation Table Base Control Register)
58	bic	r0, r0, #0x37
59	orr	r0, r0, #0x20		@ disable TTBR1
60	mcr	p15, 0, r0, c2, c0, 2
61
62	orr	r0, r12, #0x8		@ Outer Cacheability for table walks: WBWA
63	mcr	p15, 0, r0, c2, c0, 0   @ TTBR0
64
65	mov	r0, #0
66	mcr	p15, 0, r0, c8, c7, 0	@ invalidate TLBs
67
68	mov	r0, #-1			@ manager for all domains (No permission check)
69	mcr	p15, 0, r0, c3, c0, 0   @ DACR (Domain Access Control Register)
70
71	dsb
72	isb
73	/*
74	 * MMU on:
75	 * TLBs was already invalidated in "../start.S"
76	 * So, we don't need to invalidate it here.
77	 */
78	mrc	p15, 0, r0, c1, c0, 0	@ SCTLR (System Control Register)
79	orr	r0, r0, #(CR_C | CR_M)	@ MMU and Dcache enable
80	mcr	p15, 0, r0, c1, c0, 0
81
82	mov	pc, lr
83ENDPROC(enable_mmu)
84
85/*
86 * For PH1-Pro4 or older SoCs, the size of WAY is 32KB.
87 * It is large enough for tmp RAM.
88 */
89#define BOOT_RAM_SIZE	(SZ_32K)
90#define BOOT_RAM_BASE	((CONFIG_SPL_STACK) - (BOOT_RAM_SIZE))
91#define BOOT_WAY_BITS	(0x00000100)   /* way 8 */
92
93ENTRY(setup_init_ram)
94	/*
95	 * Touch to zero for the boot way
96	 */
970:
98	/*
99	 * set UNIPHIER_SSCOQM, UNIPHIER_SSCOQAD, UNIPHIER_SSCOQSZ, UNIPHIER_SSCOQWN in this order
100	 */
101	ldr	r0, = 0x00408006	@ touch to zero with address range
102	ldr	r1, = UNIPHIER_SSCOQM
103	str	r0, [r1]
104	ldr	r0, = BOOT_RAM_BASE
105	ldr	r1, = UNIPHIER_SSCOQAD
106	str	r0, [r1]
107	ldr	r0, = BOOT_RAM_SIZE
108	ldr	r1, = UNIPHIER_SSCOQSZ
109	str	r0, [r1]
110	ldr	r0, = BOOT_WAY_BITS
111	ldr	r1, = UNIPHIER_SSCOQWN
112	str	r0, [r1]
113	ldr	r1, = UNIPHIER_SSCOPPQSEF
114	ldr	r0, [r1]
115	cmp	r0, #0			@ check if the command is successfully set
116	bne	0b			@ try again if an error occurs
117
118	ldr	r1, = UNIPHIER_SSCOLPQS
1191:
120	ldr	r0, [r1]
121	cmp	r0, #0x4
122	bne	1b			@ wait until the operation is completed
123	str	r0, [r1]		@ clear the complete notification flag
124
125	mov	pc, lr
126ENDPROC(setup_init_ram)
127
128#define DEVICE	0x00002002 /* Non-shareable Device */
129#define NORMAL	0x0000000e /* Normal Memory Write-Back, No Write-Allocate */
130
131ENTRY(create_page_table)
132	ldr	r0, = DEVICE
133	ldr	r1, = BOOT_RAM_BASE
134	mov	r12, r1			@ r12 is preserved during D-cache flush
1350:	str	r0, [r1], #4		@ specify all the sections as Device
136	adds	r0, r0, #0x00100000
137	bcc	0b
138
139	ldr	r0, = NORMAL
140	str	r0, [r12]		@ mark the first section as Normal
141	add	r0, r0, #0x00100000
142	str	r0, [r12, #4]		@ mark the second section as Normal
143	mov	pc, lr
144ENDPROC(create_page_table)
145